JPH04328849A - Package for semiconductor device use - Google Patents

Package for semiconductor device use

Info

Publication number
JPH04328849A
JPH04328849A JP3098409A JP9840991A JPH04328849A JP H04328849 A JPH04328849 A JP H04328849A JP 3098409 A JP3098409 A JP 3098409A JP 9840991 A JP9840991 A JP 9840991A JP H04328849 A JPH04328849 A JP H04328849A
Authority
JP
Japan
Prior art keywords
board
semiconductor device
qfp
package
land
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3098409A
Other languages
Japanese (ja)
Other versions
JP2922668B2 (en
Inventor
Tomomi Hamada
浜田　智美
Seiji Takemura
竹村　誠次
Eitaro Nagai
永井　英太郎
Masataka Kawai
河井　優孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ryoden Kasei Co Ltd
Mitsubishi Electric Corp
Original Assignee
Ryoden Kasei Co Ltd
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ryoden Kasei Co Ltd, Mitsubishi Electric Corp filed Critical Ryoden Kasei Co Ltd
Priority to JP3098409A priority Critical patent/JP2922668B2/en
Publication of JPH04328849A publication Critical patent/JPH04328849A/en
Application granted granted Critical
Publication of JP2922668B2 publication Critical patent/JP2922668B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To facilitate a conductor wiring to the outer peripheral parts of a board, that is, a wiring to external terminals and lands for mounting use, which are provided on the board. CONSTITUTION:In a package for a semiconductor device of a structure, wherein land parts 3 arranged on a board 2 are soldered to terminals of a QFP 1 which is mounted on the board 2, the land parts 3 are arranged in a state slanted at an angle of 45 degrees to the edge sides of the board 2.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】この発明は、ＰＧＡ（ピングリッ
ドアレイ）の基板構造及びランド形成に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PGA (pin grid array) substrate structure and land formation.

【０００２】0002

【従来の技術】図２（ａ），（ｂ）は従来の半導体装置
用パッケージの平面図と側面図であり、図において、１
はＱＦＰ、２は基板、３はランド部、４は外部端子であ
り、基板２上にランド部３を介しＱＦＰ１を半田付し、
このＱＦＰ１の端子と基板の他面に格子状に配列された
外部端子４とが基板２上にあらかじめ配線された導体（
図示せず）によって接続されている。なお外部端子４は
半田を介して基板２に取り付けられている。2(a) and 2(b) are a plan view and a side view of a conventional semiconductor device package.
is the QFP, 2 is the board, 3 is the land part, and 4 is the external terminal. QFP1 is soldered onto the board 2 via the land part 3,
The terminals of this QFP 1 and the external terminals 4 arranged in a grid on the other side of the substrate are connected to conductors (
(not shown). Note that the external terminals 4 are attached to the substrate 2 via solder.

【０００３】0003

【発明が解決しようとする課題】従来の半導体装置用パ
ッケージは以上のように構成されており、基板の小型化
，外部端子の増加により、端子間ピッチが狭くなり、基
板外周部においてはＱＦＰの端子と外部端子を接続する
基板上の導体配線が困難になるという問題点があった。[Problems to be Solved by the Invention] Conventional semiconductor device packages are constructed as described above, and as the substrate becomes smaller and the number of external terminals increases, the pitch between the terminals becomes narrower, and QFP There was a problem in that it became difficult to conduct conductor wiring on the board to connect the terminals and external terminals.

【０００４】この発明は上記のような問題点を解消する
ためになされたもので、基板外周部への導体配線を容易
にすることを目的とする。The present invention has been made to solve the above-mentioned problems, and its object is to facilitate conductor wiring to the outer periphery of the substrate.

【０００５】[0005]

【課題を解決するための手段】この発明に係る半導体装
置用パッケージは、基板上にＱＦＰの端子を半田付する
ランド部を、基板の各辺に対して４５度の角度で配置し
たものである。[Means for Solving the Problems] A package for a semiconductor device according to the present invention has land portions on which QFP terminals are soldered on a substrate, arranged at an angle of 45 degrees with respect to each side of the substrate. .

【０００６】[0006]

【作用】この発明においては、基板外周部の外部端子と
ＱＦＰ端子半田付ランドとの導体配線を容易にすること
ができる。According to the present invention, conductor wiring between the external terminal on the outer periphery of the board and the QFP terminal soldering land can be facilitated.

【０００７】[0007]

【実施例】以下、この発明の一実施例を図について説明
する。図１において、ＱＦＰ１を半田付するランド３が
基板２の各辺と４５度の角度で配置されており、その上
にＱＦＰ１が半田付されている。これにより、基板外周
部の外部端子４とＱＦＰ半田付ランド３との導体配線が
容易にできるものとなる。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, lands 3 to which the QFP 1 is soldered are arranged at an angle of 45 degrees to each side of the substrate 2, and the QFP 1 is soldered thereon. Thereby, conductor wiring between the external terminal 4 and the QFP soldering land 3 on the outer periphery of the board can be easily performed.

【０００８】[0008]

【発明の効果】以上のようにこの発明によれば、ＱＦＰ
半田付ランドを基板に対して４５度の位置に形成するこ
とによって、ＱＦＰ半田付ランドと基板外周部の外部端
子との導体配線を容易に行えるという効果が得られる。[Effects of the Invention] As described above, according to this invention, QFP
By forming the soldering land at a position of 45 degrees with respect to the board, it is possible to easily conduct conductor wiring between the QFP soldering land and the external terminal on the outer periphery of the board.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】この発明の一実施例を示す平面図である。FIG. 1 is a plan view showing an embodiment of the present invention.

【図２】従来の半導体装置用パッケージの平面図（ａ）
とその側面図（ｂ）である。[Fig. 2] Plan view (a) of a conventional semiconductor device package
and its side view (b).

【符号の説明】[Explanation of symbols]

１　　　　ＱＦＰ ２　　　　基板 ３　　　　ＱＦＰ半田付ランド ４　　　　外部端子 1 QFP 2　　　　Substrate 3 QFP soldering land 4 External terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　４角形の基板の一面側にＱＦＰパッケ
ージを取り付けるランド及び配線が形成され、かつ他面
に複数の外部端子を突設してなる半導体装置用パッケー
ジにおいて、上記パッケージ取付用ランドを、基板の各
辺に対して４５度の角度で斜めに配置することにより、
外周部にある外部端子への配線を容易にしたことを特徴
とする半導体装置用パッケージ。1. A semiconductor device package in which a land and wiring for mounting a QFP package are formed on one side of a rectangular substrate, and a plurality of external terminals protrude from the other side, wherein the land for mounting the package is formed on the other side. , by placing it diagonally at a 45 degree angle to each side of the board,
A semiconductor device package characterized by easy wiring to external terminals on the outer periphery.
JP3098409A 1991-04-30 1991-04-30 Package for semiconductor device Expired - Lifetime JP2922668B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3098409A JP2922668B2 (en) 1991-04-30 1991-04-30 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3098409A JP2922668B2 (en) 1991-04-30 1991-04-30 Package for semiconductor device

Publications (2)

Publication Number Publication Date
JPH04328849A true JPH04328849A (en) 1992-11-17
JP2922668B2 JP2922668B2 (en) 1999-07-26

Family

ID=14219037

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3098409A Expired - Lifetime JP2922668B2 (en) 1991-04-30 1991-04-30 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JP2922668B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007129046A (en) * 2005-11-02 2007-05-24 Murata Mfg Co Ltd Mounting structure of capacitor array
US9847299B2 (en) 2014-09-30 2017-12-19 Murata Manufacturing Co., Ltd. Semiconductor package and mounting structure thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007129046A (en) * 2005-11-02 2007-05-24 Murata Mfg Co Ltd Mounting structure of capacitor array
US9847299B2 (en) 2014-09-30 2017-12-19 Murata Manufacturing Co., Ltd. Semiconductor package and mounting structure thereof

Also Published As

Publication number Publication date
JP2922668B2 (en) 1999-07-26

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