JPH01228155A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the short-circuit between adjacent connecting wires and to contrive an increase in the number of the connecting wires by a method wherein conductor ribbons are formed integrally with a semiconductor chip on the peripheral part of the chip, electrode pads are arranged on the insides of these conductor ribbons and the ribbons and bonding wires, which are each connected to the electrode pad, are respectively provided extendedly in a state that a vertical distance exists between the ribbons and the bonding wires. CONSTITUTION:Parts of a circuit of a semiconductor chip 1 are connected electrically to the side of a PGA substrate 11 by conductor ribbons 2 and the residual parts of the circuit are connected to the side of the substrate 11 by bonding wires 4. The ribbons 2 are provided extendedly on almost the same plane as the surface of the chip 1, the wires 4 are provided extendedly in the form of a loop at positions higher than the surface of the chip and the ribbons 2 and the wires 4 respectively make the chip 1 connect electrically with the substrate 11. Accordingly, a trouble that both interfere with each other and are short-circuited is scarcely generated. Thereby, even in case the number of wires to be used for an electrical connection with the substrate 11 is increased in response to an increase in the density of the chip 1, this way can easily deal with this and can correspond to an increase in the density and the multipin formation of a semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device with high density and a large number of bins.

[Conventional technology]

Conventionally, for example, in a pin grid array (PGA) type semiconductor device, wiring provided on a PGA substrate and electrode pads of a semiconductor chip mounted on a second PGA substrate are connected with bonding wires, and pins for external connection on the PGAI board ψ are connected. Makes electrical connections with semiconductor chips. In recent years, as the density of this type of semiconductor chip has increased, the number of pins has increased, and the number of bonding wires connecting the semiconductor chip and the PGA substrate has also tended to increase. For this reason, on the semiconductor chip side, a large number of electrode pads are arranged in a staggered manner, that is, in two rows and alternately, and bonding wires are connected alternately to inner and outer positions to cope with this increase in pin count. There is.

[Problem to be solved by the invention]

In the conventional semiconductor device described above, even if the electrode pads are arranged in a staggered manner, the pitch between adjacent bonding wires to be connected is 1/2 compared to when the electrode pads are arranged in one row, and the pitch between adjacent bonding wires is Short circuit accidents are more likely to occur between the two. Therefore, as a result, it is necessary to take a larger pitch between adjacent electrode pads than in the case of one row, and there is a problem that it is not possible to cope with higher density and increase in the number of pins of semiconductor devices.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can easily accommodate higher density and an increased number of pins.

[Means for Solving the Problems] The semiconductor device of the present invention has a large number of ribbon pads arranged around the chip mounting portion of the substrate, and a large number of wire pads arranged outside of the pads, and the semiconductor chip has a large number of wire pads arranged around the chip mounting portion of the substrate. A conductor ribbon is integrally formed, a large number of electrode pads are arranged inside this conductor ribbon, this conductor ribbon is directly connected to the ribbon pad, and the electrode pad is connected to the wire pad with a bonding wire. It is said that

[Effect]

In the above-described configuration, the conductor ribbon and the bonding wire are vertically spaced apart from each other, thereby preventing mutual interference and short-circuiting between adjacent connection wires, thereby improving the performance of the semiconductor device. Supports higher density and multiple pins.

〔Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a cross-sectional view of an embodiment in which the present invention is applied to a PGA type semiconductor device, FIG. 2 is a perspective view of a semiconductor chip, and FIG.
The figure is a partially cutaway enlarged plan view.

As shown in the figure, a plurality of conductor ribbons 2 which are directly connected to a part of the circuit wiring 1a are integrally connected to the peripheral part of the surface of the semiconductor chip 1, and a large number of conductor ribbons 2 are connected to the inside of these conductor ribbons 2. electrode pads 3 are arranged. This conductor ribbon 2 can be used, for example, by tape automated bonding (
It is formed by a method called TAB). That is, conductor leads are adhered to a film-like tape in advance, and the semiconductor chip 1 is directly bonded to this tape.
In this method, the tape is then peeled off, leaving conductor leads on the semiconductor chip 1 to make connections.

This semiconductor chip 1 is mounted and fixed in the center recess of the PGA substrate 11 with silver paste 5, and the PGA substrate 1
The conductor ribbon 2 is attached to the lead pad 12 formed on the conductor ribbon 1.
are directly connected by thermocompression bonding method, etc. Further, a wire pad 13 is formed outside the lead pad 12, and the wire pad 13 and the electrode pad 3 of the semiconductor chip 1 are connected by a bonding wire 4.

Note that 14 is the lead pad 12. The external connection pin 6 connected to the wire pad 13 is a cap.

According to this configuration, a part of the circuit of the semiconductor chip 1 is electrically connected to the PGA board 11 side by the conductor ribbon 2,
And the remaining circuit part is connected to P by bonding wire 4.
It is connected to the GA1 board 11 side. The conductor ribbon 2 is extended in substantially the same plane as the surface of the semiconductor chip 1,
The bonding wire 4 is extended in a loop shape at a position higher than the chip surface, and is connected to the semiconductor chip 1 and the PGA substrate 11, respectively.
Since the two are electrically connected, there is almost no chance of interference and short circuits between the two.

In particular, in this embodiment, since the electrode pad 3 is arranged in the middle of the pitch of the conductor ribbon 2, the conductor ribbon 2 and the bonding wire 4 are also extended with a half-pitch shift.
It becomes possible to more effectively prevent mutual short circuits.

As a result, as the density of the semiconductor chip 1 increases, the PGA
Even if the number of electrical connection lines with the substrate 11 increases, this can be easily handled, and it is possible to cope with higher density and multi-pin semiconductor devices.

FIG. 4 shows another embodiment of the present invention, which shows a semiconductor device in which a plurality of semiconductor chips are mounted on two substrates.

In the figure, the substrate 21 is made of alumina ceramic,
A conductor pattern is formed on this surface using thick film technology. Semiconductor chip mounting portions are defined at two locations on this substrate 21, and lead pads 22 are formed around each chip mounting portion using a portion of the conductive pattern. Also,
Wire pads 23 are formed outside these lead pads 22 .

Then, the semiconductor chip 1 is mounted and fixed on the chip mounting portion, and its conductor leads 2 are connected to the lead pads 22, and the electrode pads 3 are connected to the wire pads 23 by bonding wires 4.

Also in this configuration, each semiconductor chip 1 and substrate 21 are electrically connected by conductor leads 2 and bonding wires 4, respectively, and on the other hand, conductor ribbon 2 and bonding wire 4 are vertically spaced apart to prevent short circuits between them. Since this is prevented, it is possible to easily respond to higher density semiconductor devices and the use of multiple pins.

Note that the present invention can be similarly applied to a semiconductor device equipped with three or more semiconductor chips.

[Effects of the Invention] As explained above, the present invention includes integrally forming a conductor ribbon around the periphery of a semiconductor chip, arranging electrode pads inside the conductor ribbon, and bonding wires connected to the conductor ribbon and the electrode pads. and extend vertically with a gap between them, so that short circuits between adjacent connection wires can be prevented.
By increasing the number of connection lines that electrically connect the semiconductor chip and the substrate, it is possible to easily achieve higher density of the semiconductor device and the use of multiple pins.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is a perspective view of a semiconductor chip, FIG. 3 is a partially cutaway enlarged plan view of the semiconductor device of FIG. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor chip, 1a... Circuit, 2... Conductor ribbon, 3... Electrode pad, 4... Bonding wire, 5... Silver paste, 6... Cap, 11...
...PGA board, 12... Ribbon pad, 13...
・Wire pad, 14...External connection bin, 21・
...Alumina ceramic substrate, 22... Ribbon pad, 23... Wire pad. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. In a semiconductor device in which a semiconductor chip is mounted on a substrate and the substrate and the semiconductor chip are electrically connected, the substrate has a plurality of ribbon pads around the chip mounting portion and a plurality of wire pads on the outside thereof. The semiconductor chip has a plurality of conductor ribbons integrally formed on its periphery, a plurality of electrode pads are arranged inside the conductor ribbon, and the conductor ribbons are directly connected to the ribbon pads. . A semiconductor device, characterized in that an electrode pad is connected to the wire pad by a bonding wire.