JPH0432926A - Information processor - Google Patents

Abstract

PURPOSE:To improve the throughput by selecting a delay time matching the information processing time required for the output of a selective means from inside to outside a chip, dividing an external memory into pipeline stages according to a pipeline control signal outputted from an internal data transfer control circuit, and accessing them. CONSTITUTION:When an operation code for accessing the external memory OM by decoders Decode1 - Decode3 according to the decoding result of packet data is provided, selective means SELECT1 - SELECT3 select delay times matching the information processing time for the output from inside to outside the chip. Therefore, the external memory is divided into plural pipeline stages according to pipeline control signals (latch signal) outputted by internal data transfer control circuits C1 - C4 and accessed. Consequently, the throughput accompanying the access to the external OM is improved and the time difference between access to the memory in the chip and access to the memory outside the chip is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention particularly relates to an information processing device using a pipeline method.

[Prior Art] In an information processing device (see Japanese Unexamined Patent Publication No. 63-204355), data is transferred between pipeline stages using a handshake method, and the average data transfer time between each pipeline section is varied. A data processing apparatus shown in FIG. 6 has been proposed to improve the processing rate (see Japanese Patent Application No. 1-30611).

FIG. 6 is a block diagram illustrating the configuration of a conventional data processing device.

The circuit in this figure includes a transfer control circuit Cl-C5, arithmetic processing elements LOGICI, LOGIC2, and a delay circuit Delayl.
, Delay2. Decoder Decodel, Dec
ode2. It is composed of data latches LATCHI to LATCH3.

When the transfer request signal S1 is input to the transfer control circuit CI from the left end of the figure, the transfer control circuit C1 transfers the data latch LATC.
Generates a latch signal to HI and latches the packet input from the left end of the figure. Arithmetic processing element LOG I C1
The information processing time is such that the transfer request signal Sl is transferred to the transfer control circuit C1.
This is the time from input to the next stage transfer control circuit C2.

Among the packets latched by the data latch LATCHI, one of the delay elements represented by delay circuits Dll-Dnl having different delay times depending on the value of the operation code (OPC) is selected.

In this way, the transfer request signal S1 input to the transfer control circuit C1 is input to the transfer control circuit C2 after the delay time of the delay circuit selected by the operation code (OPC). When the transfer request signal S1 is input to the transfer control circuit C2, the transfer control circuit C2 generates a latch signal to the data latch LATCH2. As a result, the calculation processing element LOG
The information result at IC1 is latched into data latch LATCH2.

Thereafter, information processing is similarly executed in the arithmetic processing element LOGIC2.

[Problems to be Solved by the Invention] Considering the case where a memory is accessed by a vibrating line in a conventional information processing device, it is necessary to make processes such as memory read and write correspond to processes between latches. I'm going to go there. At this time, assuming that a large capacity memory is accessed in a system integrated on one chip, there is a limit to the memory capacity that can be mounted on the chip, so the structure is such that the insufficient memory capacity is stored on the top of the chip. is possible. At that time, there is a large difference in access time when accessing the inside and outside of the chip, so it is better to select delay circuits that are suitable for the processing time for each inside and outside, as in the conventional example. . However, in this case, if a packet accessing the external memory arrives, the throughput will drop significantly.

In other words, even though the delay in data transfer between latches can be made variable, if an unnecessarily large delay is inserted as in this case, the throughput of the entire system will be significantly reduced.

[Means for Solving the Problems 1] The information processing device according to the present invention includes a vibe line for temporarily storing intermediate information of processing in each pipeline stage when processing is divided into a plurality of vibe line stages. Data latches according to the number of stages, a data transfer control circuit that transfers data between each data latch using a handshake method, and a delay time switchable on the transfer control signal line to adjust the propagation delay of this data transfer control circuit. a delay element, a selection means for selecting a delay time by the delay element according to the processing time required for the information processing element in the Vibrine stage determined by the value of input data, and when accessing data to the outside of the chip, It is provided with a memory that is divided into a plurality of pipeline stages and accessed based on an internal vibe line control signal.

[Operation] In the present invention, when the selection means has an operation code for accessing the external memory according to the decoding result of the packet data, the selection means reduces the delay time that exceeds the information processing time for outputting from inside the chip to the outside. Based on the pipeline control signal outputted from the internal data transfer control circuit, the external memory is divided into a plurality of pipeline stages and accessed, thereby improving the throughput associated with accessing the external memory.

Embodiment 1 FIG. 1 is a block diagram illustrating the configuration of an information processing apparatus showing an embodiment of the present invention, and the same components as in FIG. 6 are given the same reference numerals.

The circuit in this diagram includes transfer control circuits 01 to C4 and delay circuit D.
elayl ~Delay3. Decoder DeCOde1
~DeCOde3. Data latch LATCHI ~ LA
It is composed of TCH6. Note that the one-dot diagonal line in the figure indicates the boundary line between the inside and outside of the chip, with the upper side being the outside of the chip and the lower side being inside the chip. OM is external memory,
5ELECTI to 5ELECT3 are selectors constituting selection means, and IM is an internal memory.

In the information processing apparatus configured as described above, when an operation code for accessing the external memory OM according to the decoding result of the packet data by the decoders Decode 1 to Decode 3 is provided, the selection means (in this embodiment, the selector 5ELECTI) is used. ~5ELECT3)
selects a delay time commensurate with the information processing time for output from inside the chip to the outside, and outputs a pipeline control signal (latch signal in this embodiment) from an internal data transfer control circuit (transfer control circuits 01 to C4). Based on the above, the external memory has multiple pipeline stages (in this embodiment, a latch receives output data from the chip in response to access to the external memory OM, and a latch receives data output from the chip in response to access to the external memory OM, and data is input to the chip as a result of accessing the external memory OM). external memory OM.
It is possible to improve the throughput associated with access, and to further reduce the time difference between accessing memory inside the chip and accessing memory outside the chip. A detailed explanation will be given below based on FIG. 1.

When the transfer request signal S1 is input to the transfer control circuit C1 from the left side of the figure, CI generates a latch signal to the data latch LATCHI, and latches the packet input from the left side of the figure. For example, in the first stage, the information processing time between latches is the time from when the transfer request signal S1 is input to the transfer control circuit C1 to when it is input to the next transfer control circuit C2. Therefore, based on the result of decoding the operational code (OPC) value of the packet latched by the data latch LATCHI by the decoder Decode4, the delay circuit D having a delay time corresponding to the information processing time required to process the packet is determined. II to I) nt must be selected by the selector 5 ELECT 1.

Similarly, the second. In the third pipeline stage, a delay circuit is also selected in order to obtain the information processing time necessary to process the packet.

Next, the case of accessing the external memory OM will be explained.

When the opcode OPC of the packet latched in the data latch LATCH1 is decoded by the decoder Decode 1, in this case it has the opcode OPC that accesses the external memory OM, so the n control lines of the decoding result are one specific line. delay circuits DIl to Dt+ are activated to obtain the information processing time necessary for the processing.
Select only one 1 with selector 5ELECT 1. The information processing time required for external memory access at this stage is the time required for packet data to exit the chip via an output buffer within the chip. The packet data output outside the chip is transferred to a data latch LATC outside the chip by a latch signal generated by the transfer control circuit C2.
Latch it to H5.

Also in the second pipeline stage, the operation code OP of the packet latched in data latch LATCH2
C is decoded by the decoder Decode 2. Since it has an operation code OPC that accesses the external memory OM, selector 5ELECT only one delay circuit ILz~Drl to obtain the information processing time necessary for that process.
Select with 2. The information processing time required for accessing the external memory OM at this stage is the time itself for accessing the external memory OM. This time is
It differs depending on the type of memory used for M, and whether it is memory writing or memory reading.

Packet data obtained by accessing the external memory OM is latched into a data latch LATCH6 outside the chip by a latch signal generated by the transfer control circuit C3.

Also in the third pipeline stage, the operation code OP of the packet latched in data latch LATCH3
C is decoded by the decoder Decode 3. Since it has an operation code OPC that accesses the external memory OM, only one selector 5ELEC is used for delay circuits Dos to Dni to obtain the information processing time necessary for that process.
Select with T3.

The information processing time required for accessing the external memory OM at this stage is the time required for external packet data to be input into the chip from outside the chip via the input buffer within the chip.

Next, the operation when accessing the internal memory IM will be explained. Decode the operation code OPC of the packet latched in data latch LATCH1
When decoding with 1, in this case, since it has an opcode OPC that accesses the internal memory IM, only a specific one of the n control lines of the decoding result is active,
Delay circuit D to obtain the information processing time necessary for the processing
Select only one item ~D n+ with selector 5 ELECT 1. The information processing time required for accessing the internal memory IM at this stage is the time required for packet data to be latched and output from ATCH1, and normally no delay is required.

Also in the second pipeline stage, the operation code OP of the packet latched in data latch LATCH2
C is decoded by the decoder Decode 2. Since it has an opcode OPC that accesses the internal memory IM, only one selector 5ELECT is selected for delay circuits I) 1m to D to obtain the information processing time necessary for the processing.
Select with 2. The information processing time required for accessing the internal memory IM at this stage is the time itself for accessing the internal memory IM. This time is
It is shorter than when accessing M.

Also in the third pipeline stage, the operation code OP of the packet latched in data latch LATCH3
C is decoded by the decoder Decode 3. Since it has an operation code OPC that accesses the internal memory IM, only one selector 5ELEC is used for delay circuits DI3 to D03 to obtain the information processing time necessary for that process.
: Select with T3. The information processing time required for accessing the internal memory IM at this stage is the time during which packet data is being output from the data latch LATCH3, and normally no delay is required.

Next, the transfer control circuit will be explained. The transfer control circuits 01 to C4 used in this embodiment are of a self-synchronization type, and as shown in FIG. 2, data transfer is controlled by handshake signals of 5END and ACK. That is, the 5END output, which is a data transfer request to the next stage, becomes active only when the 5END input, which indicates a data transfer request from the previous stage, is active and the ACK input, which indicates that the next stage is vacant, is also active. At this time, A
The CK output is in a disabled state indicating a busy state,
In this state, the transfer control circuits 01 to C4 return to the active state after their own delay time. Self-synchronous data transfer is realized by controlling the data latch using the 5END outputs of the transfer control circuits C1 to C4. The details of the transfer control circuits 01 to C4 are described in detail in the data control circuit of Japanese Patent Application No. 62-36551, so the explanation will be omitted.

In the above embodiment, the case where the delay circuit ~Dn2 is constructed by connecting variable delay elements in parallel as shown in FIG. The same effects can be achieved.

Also, for the transfer control circuits 01 to C4, C, Mead,
Co-authored by Conch1i rINTRODUcTION T
o It can also be realized using MILLER's C element using a 4-cycle signal in Chapter 7 of VLSI SYSYTEMS J.

Furthermore, in the above embodiment, memory access was performed using only one stage of the second vibrating stage, but the processing may be divided into multiple stages, such as by further dividing the pipeline stage for address decoding. By doing so, it is possible to further improve the throughput.

FIG. 5 is a flowchart illustrating an example of a memory access control procedure in the information processing apparatus according to the present invention. Note that (11 to (12)) indicate each step.

First, in the first pipeline stage, the decoder De
code 1 decodes the opcode OPC1)
Determine whether the decoded access destination is the internal memory IM 2) If YES, selector 5 ELECT
In step 1, select a delay circuit for accessing the internal memory IM (3), proceed to step (5) and subsequent steps, and if NO, select a delay circuit for accessing the external memory 90M (4).

Next, in the second pipeline stage, decoder D
ecode 2 decodes the opcode opc 5)
, determine whether the decoded access destination is the internal memory IM 6), and if YES, selector 5 ELECT
In step 2, select a delay circuit for accessing the internal memory IM (7), proceed to step (9) and subsequent steps, and if NO, select a delay circuit for accessing the external memory 90M (8).

Next, in the third pipeline stage, decoder D
ecode 3 decodes the opcode opc9)
, determine whether the decoded access destination is internal memory M (lO), and if YES, selector 5ELECT
In step 3, a delay circuit for accessing the internal memory IM is selected (11), and the process is terminated.If No, a delay circuit for accessing the external memory 90M is selected (12), and the process is terminated.

〔Effect of the invention〕

As explained above, when processing is divided into multiple pipeline stages, the present invention provides data latches corresponding to the number of pipeline stages for temporarily storing intermediate information of processing in each pipeline stage, and A data transfer control circuit that transfers data between data latches using a handshake method, a delay element whose delay time can be switched on the transfer control signal line to adjust the propagation delay of this data transfer control circuit, and the value of input data. a selection means that selects a delay time using a delay element according to the processing time required for an information processing element within the pipeline stage determined by; Since the memory is divided into multiple pipeline stages and accessed, even when a packet accessing the external memory arrives, there is no need to increase the delay time associated with data transfer between each internal data latch. This has the effect of suppressing a drop in throughput even when accessing external memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the configuration of an information processing apparatus showing an embodiment of the present invention, FIG. 2 is a schematic diagram illustrating data transfer processing in the transfer control circuit shown in FIG. 1, and FIG. , FIG. 4 is a block diagram illustrating another configuration of the delay circuit shown in FIG. 1, FIG. 5 is a flowchart illustrating an example of a memory access control procedure in the information processing apparatus according to the present invention, and FIG. FIG. 1 is a block diagram illustrating the configuration of a conventional data processing device. In the figure, 01 to C4 are transfer control circuits, Delay
-Delay3 is a delay circuit, Decode 1~Dec
ode 3 is a decoder, LATCH1 to LATCH6 are data latches, OM is external memory, 5ELECTI to 5
ELECT3 is selector, IM is internal memory, D II
~D nll D +2~D n21 D +a~D
ns is a delay circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts. Figure 2 Figure 3 Figure 4 Agent Masuo Oiwa (2 others)

Claims (1)

[Claims] In an information processing device using a pipeline processing method, when processing is divided into multiple pipeline stages, a data latch corresponding to the number of pipeline stages is used to temporarily store intermediate information of processing in each pipeline stage. , a data transfer control circuit that transfers data between each data latch using a handshake method, a delay element whose delay time can be switched on the transfer control signal line to adjust the propagation delay of this data transfer control circuit, and an input circuit. selection means for selecting a delay time by the delay element according to the processing time required for the information processing element within the pipeline stage determined by the data value; 1. An information processing device comprising: a memory that is divided and accessed into a plurality of pipeline stages based on a control signal.