JPH0433055B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a timing clock generator,
In particular, the present invention relates to a timing clock generator that generates a high-speed timing clock suitable for electronic equipment that uses a plurality of timing clocks.

[Background of the invention]

Conventional timing clock generators use a ring counter to generate multiphase timing pulses using a reference frequency and its opposite polarity, as described in "Computer Design Technology []" by Hiroyuki Watanabe, published by CQ Publishing Co., Ltd., pages 156-157. is occurring. However, the speed of the flip-flop constituting the ring counter must respond faster than twice the reference frequency, and there is a limit to providing a multiphase clock with a high speed machine cycle.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to increase the speed of a timing clock, which is limited by the operating speed limit of a flip-flop used in a conventional timing clock generator.

[Summary of the invention]

The present invention focuses on the fact that the phase difference between each phase of the timing generator corresponds to one cycle of the basic clock, and that the basic clock has a duty of 50%, and prepares two timing generators.
By inputting the basic clock to one unit and the reverse phase of the basic clock to the other, the multi-phase timing clocks (pulses) generated from the two timing generators are converted to 1/2 wavelength of the basic clock. Shift by a minute. At this time, the two timing generators are synchronized by a synchronization circuit. Among the two timing generators, the timing clock of the former timing generator is ORed with the timing clocks (i-phase and i+n/2-phase pulses) having a phase difference of 1/2 machine cycle, This is assumed to be an even phase timing clock. In addition, the timing clocks of the latter timing generator have a phase difference of 1/2 machine cycle (i-phase and i+n/2-phase pulses).
OR and use this as the odd-numbered phase timing clock. By combining the even-phase timing clock and the odd-phase timing clock, a timing clock with half the machine cycle and the same number of phases can be obtained compared to the conventional timing clock of one timing generator. I can do it.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail using FIGS. 1 to 3.

FIG. 1 shows the configuration of an embodiment of the present invention. This is an 8-phase clock T10 to T10 by the basic clock TS.
Timing generator 1 generates T17, and the 8-phase clock T20~ is generated by the inverted signal of the basic clock.
It consists of a timing generator 2 that generates T27, OR circuits 4 to 11 that OR the outputs of each timing generator, and a basic clock buffer circuit 3.

FIG. 2 shows a timing generator synchronization circuit. Here, 12 to 18 are circuits that synchronize the start and stop of the two timing generators, 12 is a 3-bit counter, 13 is a decoder, 14 is a buffer circuit, 15 to 17 are flip-flops, and 18 is an AND circuit. It shows. 1
9 is a timing generator 1, 21 to 24 are start and stop circuits of the timing generator 1, 21 is a 3-bit counter, 22 is a decoder, and 23 and 24 are flip-flops. Similarly, 20 is a timing generator 2,
25 to 28 are start and stop circuits of the timing generator 2, 25 is a 3-bit counter,
26 is a decoder, and 27 and 28 are flip-flops.

FIG. 3 shows waveforms at various points in the circuit of FIG. 2. CNT shows the decoding result of the decoder 13, CNT1 shows the decoding result of the decoder 22, and CNT2 shows the decoding result of the decoder 26. T10 to T17 indicate the timing clock waveforms of the timing generator 1, and T20 to T27 indicate the timing clock waveforms of the timing generator 2.

In Fig. 1, when a basic clock is input, timing generator 1 generates 8-phase timing clocks T10 to T17 for clock TS, and timing generator 2 generates 8-phase timing clocks T20 to T27 for an inverted signal of clock TS. occurs. In this case, the basic clock of timing generator 2
Since TS is delayed by 1/2 period of the basic clock compared to the basic clock TS of timing generator 1, the phase of T20 to T27 is the same as that of T10 to T17.
It is delayed by 1/2 cycle of the basic clock compared to . The output of each timing generator 1, 2 is an OR circuit 4
-11 is ORed, and this result is set as T0 to T7.

As is clear from the clock waveforms T0 to T7 in Figure 1, the outputs T10 to T7 of timing generator 1 are
T17 and timing generator 2 output T20~
By synthesizing one cycle of T27, two cycles of the 8-phase timing clock can be obtained.

In FIG. 2, timing generator 1 and timing generator 2 are started synchronously,
This circuit outputs or stops the timing clock in the order of T10, T20, T11, T21 to T17, and T27.

The counter 12 and the internal counter 21 of the timing generator 1 operate with the same basic clock TS, and the internal counter 25 of the timing generator 2 operates with the opposite phase of the basic clock.

The operation of this circuit is such that when each counter is operated by the basic clock and the asynchronous scan clock PSiCLK is input, the flip-flop 1
5 is set, and when the decoder 13 is 4, it is set in the flip-flop 16, and the decoder 13 is 1.
At this time, it is set in the flip-flop 17 and becomes the synchronization scan clock SiCLK, which is supplied to each timing generator.

Starting and stopping of each timing generator is performed by scan-in to flip-flops 23 and 27 inside the timing generator.
Flip-flops 24 and 28 are start enable flip-flops, and each timing generator starts when these flip-flops are set to "1". Flip-flops 24 and 28 are set when the outputs of internal decoders 22 and 26 of each timing generator are "0". In order to start timing generator 2 after 1/2 cycle of the basic clock after timing generator 1 starts,
Scan clock to each timing generator
The time to input SiCLK is the flip-flop 2
4 must be set, and 1/2 period of the basic clock must be the time at which flip-flop 28 is set.

For this reason, the scan clock SiCLK to each timing generator is generated at the times shown in FIG. 3 by the synchronization circuits 12 to 18 in FIG.

In the case of a stop operation, the start enable flip-flop is set to "0", and the other operations are the same as in the case of a start operation.

〔Effect of the invention〕

According to the present invention, two timing generators are provided.
By using one timing generator, the cycle of the timing clock can be reduced to 1/2 of that when using one timing generator, which has the effect of expanding the operating limits of the timing generator to the high frequency side. .

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of an embodiment of the present invention, and FIG.
This figure shows a synchronization circuit of the timing generator used in FIG. 1, and FIG. 3 is a waveform diagram of each part of the circuit in FIG. 2. 1...Timing generator, 2...Timing generator, 3...Buffer circuit, 4-11...
OR circuit.

Claims (1)

[Claims] 1 Input the basic clock of frequency o, n/
During a machine cycle of length o, different n
In a timing clock generator that generates (even) phase pulses, the basic clock is input, and a first timing clock generator that generates pulses sequentially from the 0th phase to the (n-1)th phase during the machine cycle. A timing generator receives an opposite phase signal of the basic clock as input, and generates n-phase pulses each shifted by 1/2 wavelength of the basic clock compared to each n-phase pulse generated from the first timing generator. A second timing generator generates pulses sequentially from the 0th phase to the (n-1)th phase, and the first timing generator and the second timing generator are synchronized to generate pulses sequentially from the 0th phase. and a plurality of OR circuits that OR the outputs of the i-th phase and the i+n/2-th phase of each of the timing generators, respectively, and generate n-phase pulses with a length of n/2o. A timing clock generator characterized by generating a new machine cycle.