JPH04330878A - Driving signal generating circuit of solid-state image pickup device - Google Patents

Abstract

PURPOSE:To judge whether or not the condition of the data written in a mode register and other block is normal. CONSTITUTION:Control data CD transmitted from a controller are read to a receiving shift register 1 and converted serially and in parallel. Out of the control data inputted to the receiving shift register 1, a selecting code signal is inputted to a decoder circuit 3 and a selecting circuit 9 and used to select first - nth mode registers 4-8. The remaining bit of the control data is inputted to these mode registers as the data of the mode register. In order to check the data of the mode register, the data of the mode register selected by a selecting circuit 9 are transmitted through a transmitting shift register 10 and a synthesizing circuit 11 to a deciding circuit (not shown in the figure).

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive signal generation circuit for a solid-state imaging device, and more particularly, the present invention has a plurality of mode registers for storing data of various operation modes, and a circuit for writing data to the mode registers. The present invention relates to a drive signal generation circuit for a solid-state imaging device.

0002

2. Description of the Related Art A solid-state imaging device is driven by selecting one of several operation modes such as a shutter mode and a high-speed photography mode, but it is necessary to store data related to each operation mode in advance. be. Conventionally, a drive signal generation circuit for this type of solid-state imaging device has had a configuration as shown in FIG. This drive signal generation circuit operates according to instructions from a controller (not shown), and the controller and this drive signal generation circuit are connected via control data CD, shift clock SC, and initialization signal IS. The controller then receives the reception permission signal RR generated in another block of the solid-state imaging device and transmits the control data.

Control data CD is read into a reception shift register 1 by a shift clock SC, and is subjected to serial to parallel conversion. Further, the control signal generation circuit 2 receives the shift clock SC and generates a control signal that governs the operation of the entire drive signal generation circuit. Receive shift register 1
A one-word command read into the mode register is divided into data to the mode register and a selection code signal, and the selection code signal is synthesized with the control signal generated by the control signal generation circuit 2 and the decoder circuit 3, and the first to nth mode register 4
It is decoded into a write signal to 8. Here, the initialization signal IS is set when the power is turned on and when necessary.
This is a signal for determining a certain state of this drive signal generating circuit.

FIG. 5 shows a timing chart for setting mode register data to the first to nth mode registers 4 to 8. In the illustrated example, the control data CD has an 8-bit configuration, of which 3 bits are a selection code signal and 5 bits are data to the mode register.

[0005]

[Problem to be Solved by the Invention] Data is set in the first to nth mode registers 4 to 8 as described above, but due to communication abnormality or failure between the controller and the drive signal generation circuit, the data is set as intended. The data may not be set as expected. However, in the drive signal generation circuit of the conventional solid-state imaging device described above, the state of the mode register and other blocks cannot be known. too,
The controller could not send an initialization signal to the drive signal generation circuit to establish a certain state and return it to a normal state.

Therefore, it is an object of the present invention to make it possible to recognize data abnormalities in the mode register by simply adding a simple circuit without adding new interfaces, thereby allowing the solid-state imaging device to operate normally. The objective is to improve the reliability of operation by making it possible to return to a normal state.

[0007]

[Means for Solving the Problems] A drive signal generation circuit for a solid-state imaging device of the present invention includes a reception shift register that receives control data from a controller and performs serial-to-parallel conversion, and generates a control signal from a shift clock from the controller. a control signal generation circuit, a plurality of mode registers storing various operation modes of the solid-state imaging device, and selective writing to the mode register from a selection code signal from the reception shift register and a write signal from the control signal generation circuit. a decoder circuit that generates a signal and causes write data of the receive shift register to be written to a selected mode register; and a decoder circuit that generates a signal to write write data of the receive shift register to a selected mode register; It includes a select circuit that selects based on a selection code signal from the shift register, and a transmission shift register that stores data selected by the select circuit and performs parallel-to-serial conversion.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. The circuit of this embodiment includes a select circuit 9 for selecting one of the first to nth mode registers, and a mode register data instructed by the select circuit 9 stored in the conventional circuit shown in FIG. The circuit is the same as the conventional circuit except that a transmission shift register 10 that performs direct conversion and a synthesis circuit 11 that synthesizes data stored in the transmission shift register and a reception permission signal RR are added.

In this embodiment, the method of rewriting the contents of the mode register based on the contents of control data CD from a controller (not shown) is the same as in the conventional example, and therefore its explanation will be omitted.

Since the reception permission signal RR prompting writing to the mode register is transmitted only during the vertical blanking period, reading of data from the mode register is performed using the valid video period. That is, when it is desired to know the data of the first to nth mode registers 4 to 8, the controller inputs the data of the first to nth mode registers 4 to 8 as control data CD within the effective video period.
A command is sent to transmit one set of data from the n-th mode registers 4 to 8, and the reception shift register 1 is read using the shift clock SC.

FIG. 2 is a timing chart when 3 bits of one word (8 bits) are used as a mode register selection code and 5 bits are allocated to a period for reading the contents of the mode register. The select circuit 9 selects the data of the first to nth mode registers 4 to 8 designated by the mode register selection code from the reception shift register 1 and causes the transmission shift register 10 to read the selected data. The data in the mode register is parallel-to-serial converted in synchronization with the shift clock 22 in the transmission shift register 10, combined with the reception permission signal RR in the combining circuit 11, and transmitted as a combined output CO to a determination circuit (not shown).

Here, the synthesis circuit 11 is a circuit constituted by, for example, an OR circuit, and this circuit outputs a reception permission signal RR during the vertical blanking period and a mode register during the effective video period as a synthesis output. data is output.

If it is found from the judgment result of the composite output CO that the drive signal generation circuit is malfunctioning, the controller sends an initialization signal IS to the drive signal generation circuit as shown in FIG. to fix it in a certain state and return it to its normal state. In this case, it is assumed that the data of each mode register is also set to a predetermined initial value.

FIG. 3 is a block diagram showing a second embodiment of the invention. In this embodiment, the selection function is further enhanced compared to the previous embodiment, and the state OB of other blocks can also be selected by the select circuit 9.

[0015]

[Effects of the Invention] As explained above, the present invention uses a select circuit to select data in a mode register or the state of another block, read it into a transmission shift register, and transmit this data to a determination circuit. According to the present invention, it is possible to know the reception status of control data and the status of other blocks by simply adding a simple circuit and changing the controller program without adding a new interface circuit. Become. Therefore, according to the present invention, it becomes possible to correct a state in which erroneous data is written, so that the reliability of the solid-state imaging device can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart of the drive signal generation circuit of FIG. 1.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional example.

FIG. 5 is a timing chart of a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1... Reception shift register, 2... Control signal generation circuit, 3... Decoder circuit, 4-8...
1st to nth mode registers, 9...Select circuit, 10...Transmission shift register, 11...
Synthetic circuit.

Claims (1)

[Claims] 1. A reception shift register that receives control data from a controller and performs serial-parallel conversion, a control signal generation circuit that generates a control signal from a shift clock from the controller, and a plurality of circuits that store various operation modes of the solid-state imaging device. a mode register, a selection code signal from the reception shift register and a write signal from the control signal generation circuit to generate a selection write signal to the mode register, and write data of the reception shift register to the selected mode. a decoder circuit for writing into a register; a select circuit for selecting data in one mode register or state data in another block from the plurality of mode registers according to a selection code signal from the receiving shift register; and the select circuit. 1. A drive signal generation circuit for a solid-state imaging device, comprising: a transmission shift register that stores data selected by and performs parallel-to-serial conversion.