JPS60215236A - Microcomputer - Google Patents

Abstract

PURPOSE:To share a control signal with plural instructions and to simplify the constitution of a gate circuit by attaining the transfer of data despite the difference between the data transmission and reception timings. CONSTITUTION:A data bus 1 is precharged with the timing of T1A for a microcomputer which transfers data between internal circuits by a data bus. A system clock T1B is delivered to a control signal OBD from an AND gate 26 with the timing of the T1B. While an output driver circuit 20 sends data B to the bus 1. Input gate circuits 24 and 22 fetch the data B on the bus 1 with timings of T2B and T3B and store it to circuit blocks C18 and A16. The data sent to the bus 1 is held although the data transmission timing is fixed. Thus it is possible to fetch data from the bus 1 with different timings.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a microcomputer that transfers data between internal circuits via a data bus.

(b) Prior art In general, in microcomputers, between internal circuits,
For example, when data is transferred from a predetermined register to an akimulator, the transfer instruction is executed via an internally provided multi-bit data bus. Conventionally, when sending data to a data bus,
As shown in FIG. 2 of the 44700 publication, during one machine cycle consisting of internal clocks T1 to T4, the data bus is precharged to a predetermined potential at timings TI and T3, and at the next timings T2 and T4. Data was sent to the data bus and applied to a predetermined circuit at the same time.

In such a micro combinator, for example, when a transfer instruction is executed to transfer data from a register of A to a register of B, a control signal from an instruction decoder that decodes the instruction causes A to be transferred at timing T2. It is assumed that the data in register B is sent to the data bus and taken into register B at the same timing.On the other hand, when another predetermined instruction is executed, the first half of TI and T2
The data bus is used at the timing of T3 and T in the second half.
At timing 4, it is assumed that an operation is performed to take in the data sent to the data bus from the outside or another circuit block, etc., into the C register. In this case, for example, when executing an instruction to transfer data from a person's register to a C register, in addition to a control signal that controls the timing T4 to take data into a C register, In synchronization with the sending timing T2, a control signal is required to cause the register of C to take in data at timing T2. Alternatively, when executing an instruction that transfers the data to the human register and the C register, the data sent to the data bus will disappear due to precharging at the timing of T3.
In addition to the control signal that causes the data in the human register to be sent out at timing T2 when the B register takes in data, a control signal that causes the data in the A register' to be sent out at the timing T4 when the C register takes in the data is required.

In this way, in a microcomputer in which every other timing data bus is precharged, multiple control signals are required to send out data in accordance with the timing at which other circuits take in data. When there are many circuit blocks such as registers that can transfer data, the number of control signals output from the instruction decoder increases, and the gate circuit combined with the system clock becomes complicated.

(C) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and enables data transfer even if the timing of sending data and the timing of data capture are different when executing a data transfer command. By doing so, the purpose is to share the control signals output from the instruction decoder with a plurality of instructions, reduce the number of them, and simplify the gate circuit.

B) Structure of the Invention The present invention provides a data bus consisting of a plurality of bits that performs data transfer between each part at different timings, a precharge circuit that applies a predetermined potential in advance when transferring data to the data bus, a precharge control circuit that controls the operation timing of the precharge circuit based on a control signal output from an instruction decoder that decodes the instruction when at least an instruction to transfer data is executed; When a data transfer command is executed, the data holding circuit applies data to the data bus at a timing consecutive to the timing at which the data bus is precharged, and at a subsequent timing. This configuration applies the held data to a predetermined circuit.

(e) Embodiment FIG. 1 is a partial block diagram of a one-chip microconbeater showing an embodiment of the present invention. The deniter bus (1) is an 8-bit internal bus that transfers data between internal circuits, and serves as a precharge circuit (2) and a data holding circuit (3).
) are connected. The precharge circuit (2) consists of an N-channel MO8):7 transistor (4) connected between each bit line of the data bus (1) and the power supply V0, and each gate of the MOS transistor (4) has a A control signal PRE that controls the timing of precharging the data bus (1) is commonly applied. That is, when the MOS transistor (4) is turned on, all bit lines of the data bus (1) are pulled up to the power supply VDD and held by the data holding circuit (3). The state of this data bus (1) is such that 8-bit data rFFJ (hexadecimal number) is sent out. The data holding circuit (3) is constructed by connecting a buffer (6) whose output is fed back to the input via a resistor (5) for each bit of the data bus (1).
The power supply raised by precharging is maintained, and when data is transferred, the bus driver lowers the level of the precharged vDI to the ground level according to the data to be sent, thereby increasing the voltage of the data bus (1).
Data is sent to the data holding circuit (3) and its potential is transferred to the data holding circuit (3).
is maintained. Note that the buffer (6) is composed of two stages of inverters.

The precharge control circuit (7) controls the MOS transistor (4) at the timing instructed by the control signal applied from the instruction decoder (8), and includes an OR gate (9) that outputs the control signal PRE. and selectively OR the system clocks TIA, T2A, and T3A.
AND feeding the control signal PRH via the gate (9)
Gate aωa1) α2 and AND gate (11 (11)
(Instruction decoding to control 121/
(13a4) (OR game to which a plurality of predetermined control signals are applied from (8)) (13a4) (1G) The system clock used here is TI, T2. Timings TIA, T2A, and T3A in the first half of each evening signal are used, and when an instruction that uses the data bus (1) is executed, the data bus (1) is pre-empted at a timing convenient for the execution of that instruction. To charge the system clock TIA, the control signal is output from the instruction decoder (8) when the SO instruction is executed.

T2A and T3A are selected. In particular, in the case of an instruction that transfers data from one register to another or multiple registers, the instruction decoder (8
), the data bus (1) is precharged at one timing in order to share the control signal output from the two. That is, when a data transfer instruction is executed,
Control signals AD, BD, and CD (these signals specify the circuit blocks that send out data) output from the instruction decoder (8) are applied to the OR game (13) that selects the system clock TIA. Therefore, the data bus (1) is precharged only at the TIA timing.

On the other hand, circuit block A (le), circuit block B (17)
, circuit blocks C (18 are, for example, 8-bit registers, each connected to the data bus (1) via an output driver circuit a'a (2Qaυ) and an input gate circuit.Output, Driver circuit (19cIlC1tl
lG family, each circuit block A (le9. circuit block B
(17), controls each bit of the data bus (1) based on the data of each bit of circuit block C (111), and when the data is l'', it is precharged and the power supply level is On the other hand, if the data is 10'', the power supply level (v, 1lI) is forcibly lowered to the ground level, the buffer (6) of the data holding circuit (3) is inverted, and the data is hold it. Furthermore, the timing of driving the data bus (1) to send out data is controlled by control signals OAD, OBD, and OCD, respectively. Control signals OAD, OBD, and OCD are generated at timing TI in the second half of timing TI of one machine cycle.
This is the output of the AND gate (C) (C) (5) to which the system clock TIB which becomes "1" at B is applied, and the AND
Control signals AD, BD, and CD specifying a circuit block storing data to be transferred when a transfer instruction is executed are applied from an instruction decoder (8) to the other input of the gate (c)@(5).

On the other hand, the input gate circuit (C) (foundation) receives the control signal ST
A.

Controlled by the timing of STB and 8TC', the data sent to the data bus (1) is taken into the circuit 7', lock Aαe, circuit block, /B(lη, circuit block C
(It is stored in 181. The control signal STA is stored at timing T3B in the latter half of timing T3 of one machine cycle.
It is the output of the AND gate () which is applied with the system clock T3B which becomes "1" and the control signal ST3 which specifies the circuit block Aa61 when executing the transfer command, and controls the input gate circuit (a) at the timing of T3B. Similarly, Control signal 8TB is connected to system clock TIB and circuit block B.
(It is the output of the AND gate (to) to which the control signal STI specifying lη is applied, and controls the input gate circuit (c) at the timing of TIB, and the control signal STC is the output of the system clock T2B and the circuit block C This is the output of the AND gate (7) to which the control signal ST2 specifying the trumpet is applied, and controls the input gate circuit at the timing T2B.

That is, from circuit block A (161) to circuit block B (l
When the data transfer command to η is executed, the instruction decoder (8) outputs the control signals AD and STI for one machine cycle and also outputs the control signals AD and STI to the circuit block B (17).
) to circuit block C (181), control signals BD and Sr2 are output.Furthermore, from circuit block A (16) to circuit block B (lη
When an instruction to transfer data to circuit block C (1119) is executed, control signals AD, STI, and ST2 are output.In this way, the data transfer instruction transfers the data to the circuit block that sends the data and the circuit block that receives the data. signals AD, BD, CD, or STI, Sr2, Sr that control the circuit block according to the instructions.
1 is output. In addition, the control signals AD, BD, C
As mentioned above, D is O of the precharge control circuit (7).
R game) (also applied to 13).

Next, the timing of data transfer will be explained with reference to FIGS. 2 and 3. FIG. 2 is a timing diagram when a data transfer instruction from circuit block A to circuit block C is executed. When this transfer instruction is executed,
As mentioned above, the control signals AD and Sr2 are output from the instruction decoder (8) during one machine cycle.
”.Then, the AN of the precharge control circuit (7)
(D) (In order to select and output the system clock TIA whose IQ is in the period "1" of the timing TIA, the data bus (1) is precharged at the timing of TIA, and it becomes as if the data rFFJ was sent out. .

Next, due to the system clock TIB which is in the period "l" of the timing TIB, the control signal OAD becomes g"l" at the timing of TIB, so that the output driver circuit a song 1
Circuit block A (1610A) drives the data bus (1) based on the A data and sends out the A data.

The sent A data is held by the data holding circuit (3) until the next data bus (1) is precharged. Then, at the timing of T2B, 1
1" is output as the control signal STC from the AND gate, so at the timing of T2B, the input gate circuit takes in the A data held on the data bus (1) K into the circuit block CQal. Make me remember.

On the other hand, FIG. 3 is a timing diagram when executing an instruction to transfer the same data from circuit block B (17) to circuit block A (le9 and circuit block CQ81. When this instruction is executed, 1 During a machine cycle, the instruction decoder (8) receives control signals BD, ST.
2. Sr1 is set to l". Then, the AND gate αω of the precharge control circuit (7) is connected to the system clock TIA
In order to select and output as the control signal PRE, the data bus (1) is precharged at the same timing of < and TIA as described above.

Next, the system clock TIB is outputted from the AND gate (a) as the control signal OBD at the timing of TIB.
The output driver circuit (a) sends B data to the data bus (1)
Send to. Then, at the timing of T2B, the system clock T2B is output to the control signal STC, and the input gate circuit (to) takes in the B data of the data bus (1) and stores it in the circuit block C (181).
At timing B, the system clock T3B is output to the control signal 8TA, so the input gate circuit takes in data bus (1) QB data and outputs the data to circuit block Aall.
Let G remember it. In this way, even if the timing for digging out data is fixed to one timing, the data bus (one
) is retained, so data can be taken in from the data bus (1) at different timings.

(F) Effects of the Invention As described above, according to the present invention, when executing a data transfer instruction, only one data transmission timing is required. Since it can be used for both purposes, the number of control signals is reduced and the gate circuit is simplified.

[Brief explanation of the drawing]

FIG. 1 is a partial block diagram showing an embodiment of the present invention, and FIG.
and FIG. 3 are timing diagrams when executing a data transfer command. °(l)...Data bus, (2)...Precharge circuit, (3)...Data holding circuit, (7)...
Precharge control circuit, (8)...instruction decoder, housing e...circuit block A, (1?)...
・Circuit block B, (1 cap...Circuit block C, (19
(21) (2υ...output driver circuit, (2) (23
) (Foundation)...Input gate circuit. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Shizuo Sano

Claims (1)

[Claims] 1. A data bus consisting of multiple bits that transfers data between each circuit at different timings, a precharge circuit that applies a predetermined potential in advance when transferring data to the data bus, and at least an instruction that transfers data is executed. a precharge control circuit that controls the operation timing of the precharge circuit based on a control signal output from an instruction decoder that decodes the instruction when the instruction is issued;
a data holding circuit that is connected to the data bus and holds applied data, and when a data transfer command is executed, sends data to the data bus at a timing consecutive to the timing at which the data bus is precharged. A microcomputer is characterized in that the data is applied to a predetermined circuit at a subsequent timing.