JPH0433123A - Disk controller - Google Patents

Abstract

PURPOSE:To reduce the burden of software on a host device-side by outputting a selection signal to a control circuit without recognizing which control circuit is the object of first access on the host device-side. CONSTITUTION:When a change over switch 13 is set on an ST 506-side, an address signal and the like are inputted to a disk switching control circuit 14 if a host selects a first hard disk. The disk 1 signal of H from the circuit 14 is inverted in an invertor 14a and is outputted to a selection terminal in an ST 506 control circuit 1. The circuit 1 is selected at that time and an IDE control circuit 1A inverts an L signal again whereby the signal is inputted to a selection terminal as the H signal. Thus the circuit 1A is not selected and it is detached from a system bus 2. Consequently, a command from the host is received only by the circuit 1 and it executes the command. When the host selects the second hard disk in such a state, the circuit 14 latches the disk 1 signal output to L. Consequently, the command from the host is received only by the circuit 1A and it executes the command.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a control device for a node disk, which is a terminal device for a computer.

[Conventional technology]

FIG. 4 is a block diagram of a disk control circuit for a 5T506 hard disk, and FIG. 5 is a disk control circuit for an IDD node disk. In Figure 4, (1)
is the main body of the hard disk control circuit, and the system bus (
2) according to the address, data, and control signals input through the 5T506 node disk (3), (3
) to control access. Node disk control circuit (1
), (4) is a host I/F section that inputs and outputs each signal between the system bus (3) and the circuit body (1);
(5) inputs and decodes the commands and parameters written to the host I/F unit (3) via the local bus (6), and then sends them to the HDC (Hard Disk Control).
ler) (7) The local microprocessor (8) is an ENDEC (E
ncoder/Decoder Controller
), (9), (9) G output MFM data to 5T506 hard disk (3), (3) or 5T50
6 hard disk (3), (3) and ENDE
20 pin connector to connect with C(8), (lO) is HD
Hard disk for C (7) and 5T506 (3), (
3) This is a 34-pole connector that connects the disc control signal and outputs the disc control signal.

Next, the operation will be explained. In Figure 4, when a command is written from the host to the host I/F section (4), the local microprocessor (5) in the control device decodes the command and parameters written to the host I/F section (4). Set I(DC(7)).

When the IDC (7) receives these, it executes the necessary control for reading/writing the 5T50B interface hard disk. Data flow is during write operation, host I/F
The unit (4) transfers the write data to the IDC (7) via the local bus (5), and the I(DC) sequentially converts it into NRZ data and outputs it to the ENDEC (8).ENDEC (8) converts this into MFM data and outputs it to the hard disks (3) and (3).During read operation, the data is processed in the opposite manner to the above.A 34-pole connector (10) is connected between the hard disk and the control device. Data and control signals are exchanged via the 20-pole connector (9).

On the other hand, in the case of the IDD interface (18) shown in FIG. 5, the interface between the hard disk (3a), (3a) and the host performs only address control and data direction control from the host. Figure 5 shows the IDD control circuit (
IAI) is doing this. Controls that were previously performed by the 5T506 hard disk control device, except for the above, are performed by IDD.
(AT)'s hard disk. Data and control signals are exchanged with the hard disk via a 40-pole connector (IA2).

(Problem to be solved by the invention) As described above, the conventional hard disk control device is a 5T5
It was a control device for either 0B or IDD.

For this reason, it was not possible to connect both interfaces to the system.

In order to solve the above problems, Japanese Unexamined Patent Publication No. 62-2
There is a "floppy disk control device" disclosed in Japanese Patent No. 33821, but this device selects the first floppy disk when selecting one of two types of floppy disks with different ink face specifications. A specific signal for selecting the second floppy disk and a specific signal for selecting the second floppy disk were output to the switching circuit to switch the path corresponding to each floppy disk. For this reason,
If the floppy disk and interface connected to each path line are replaced for reasons on the user side, the specific signal for selecting the floppy disk must also be changed, which increases the software burden on the host CPU.

This invention was made to solve the above problems, and it provides a disk control device that can connect hard disks with different interface specifications such as a 5T506 interface hard disk and an IDD (AT) interface in the same system. The porpose is to do.

[Means to solve the problem]

The disk control device according to the present invention includes a control circuit corresponding to each hard disk for controlling access to hard disks having different interface specifications, and a control circuit corresponding to each hard disk,
disk switching means for switching and outputting selection signals for the first and second hard disks to be accessed; switch means for arbitrarily switching and setting the hard disk to be the first access target among the hard disks; and the first access target. Deriving the selection signal of the hard disk to be arbitrarily set to the control circuit corresponding to the first access target hard disk, and deriving the other selection signal that has been switched and output to the control circuit corresponding to the second access target hard disk. The means are provided.

[Effect]

According to this invention, the user side selects the hard disk to be the first access target outputted from the disk switching means by setting which hard disk among the plurality of hard disks is to be the first access target using the switch means. The signal is led to the control circuit corresponding to the hard disk, and other selection signals that are switched and output are sent to the control port 3 corresponding to the hard disk to be accessed. c,
Because the host computer side does not recognize which hard disk is set as the first access target, the first access is set as the second access target. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In Figure 1,
(1) is the 5T506 control circuit, (18) is the IDC control circuit, (11), (11) is the 5T50B connector,
(12) is the IDD connector, (13) is the changeover switch, (14) is the disk switching control circuit, (14a
) and (14b) are inverters for signal inversion.

The S-506 control circuit (1) is equivalent to the hard disk control device shown in FIG. 4, and (IA) is equivalent to the IDC control circuit shown in FIG. Further, FIGS. 2 and 3 are configuration diagrams of the disk switching control circuit (14).

Next, the operation of this embodiment will be explained according to the above configuration.The address signal is sent to the disk switching control circuit (14).The address decoder α3') decodes the input address signal, and the unit register (13b) receives the decoded output. )
In addition, the unit register (13b) opens the gate of ``
Write the data bit of “H” in synchronization with the write signal,
Latch and output the disk 1 signal that selects the unit. The disk 1 signal of this rHJ is connected to the inverter (14
It is inverted at step a), becomes "L", and is output to the select terminal of the 5T506 control circuit (1). At this time 5T50
6 control circuit (1) is selected, but the IDC control circuit (
18) inverts the "L" signal from the changeover switch (13) again and inputs it to the select terminal as the rHJ signal, so it is not selected and the IDC control circuit (IA) is disconnected from the system bus. Therefore, only the 5T506 control circuit (1) accepts and executes commands from the host. In addition, when the host selects the second hard disk with the changeover switch (13) set to the 5T506 side, the disk changeover circuit (14) is activated by the host via the system bus (2) as described above. Input the "L" data bit together with the address indicating the third hard disk (IDC hard disk (3a)), and latch the disk 1 signal output to "L". As a result, the disk 1 signal is inverted by the inverter (14a), becomes "H", passes through the changeover switch (13), is inverted again by the inverter (14b), becomes rl, J, and becomes the IDC control circuit (18). ) is input manually to the select terminal of
Since the signal is rHJ, the 5T508 control circuit (1) is not selected and is disconnected from the system bus. Therefore, only the IDC control circuit (IA) accepts and executes commands from the host.

On the other hand, when the changeover switch (13) is set to the IDD side, the disk changeover circuit (14) selects the address for selecting the first disk and "H" as described above.
When data bits etc. are input and the disk 1 signal of "rH" is latched and output, the "H" output is sent to the inverter (14b).
It is inverted at , becomes "L", and is input to the select terminal of the IDC control circuit (IA).

On the other hand, if each signal for selecting the second gold disc is manually generated from the host, the "L" disc 1 signal is directly 5T506
It is latched and output to the select terminal of the control circuit (1). Therefore, on the host side, there is no need to recognize whether the 5T506 disk (3) or the IDC disk (3a) is selected as the first hard disk.
Each hard disk becomes executable by outputting a signal for selecting the first and second disk.

In the above embodiment, when setting the first hard disk, the hardware switch was switched to a control circuit compatible with the first hard disk, but as shown in FIG. 3, the unit register (13b) and ExOR (14d) takes the exclusive OR of the switch signal from the similar switching register (14c) and the disk 1 number from the unit register (13b), and outputs the logical output from each control circuit (1), ( It is also possible to latch output to the select terminal of 1^).

For example, when setting the 5T506 disk (3) as the first hard disk, the switch signal is latched to rH and input to ExOR (14d), and the disk 1 signal is also latched to rl (J and ExOR
When (14d) is manually input, ExOR (14d) output is “L”
” and is input only to the select terminal of the 57506 control circuit (1). Also, when the switch signal is latched to "L", the ExOR (14d) output becomes "H", and is further inverted to "L" by the inverter (14b), l0DIIJ
It is input only to the select terminal of the control circuit (IA).

Alternatively, when using the IDC disk (3a) as the first hard disk, set the switch signal to "L" and use ExOR.
(14d), and in this state, if you latch the disk 1 signal of rHJ to ExOR (14d), E
After the xOR output becomes r HJ, Inno Teichita (
14b), rl is inverted to J, and Itl[l control circuit (I
A) is manually input to the select terminal. On the other hand, when the disk 1 signal is latched as r L J and output to ExOR (14d), the ExOR output becomes "L" and is input to the select terminal of the 5T506 control circuit (1). Therefore, the settings for the first disk can be performed using a setting command from the host.

〔Effect of the invention〕

As described above, according to the present invention, control circuits corresponding to hard disks with different interface specifications are installed in the same control device, and among these control circuits, the control circuit to be accessed first can be arbitrarily set by the user at any time. In addition, the host device can output a selection signal to the control circuit that is the first access target without recognizing which control circuit is the first access target, making it an extremely versatile control device. At the same time, the software burden on the host device side can be reduced.

[Brief explanation of the drawing]

¥S1 is a block diagram of a hard disk control device according to an embodiment of the present invention, FIG. 2 is a block diagram of a disk switching circuit in this embodiment, and FIG. 3 is a block diagram of a disk switching circuit according to another embodiment. FIG. 4 is a block diagram of a hard disk control circuit for controlling 5T506, and FIG. 5 is a block diagram of a hard disk control circuit for IDD. In the figure, (1) is a 5T506 control circuit, (IA) is an IDD control circuit, (3) is a 5T506 disk, (3a
) is the IDC disk, (13) is the changeover switch, (
14) is a disk switching control circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A control circuit corresponding to each hard disk that controls access to hard disks having different interface specifications, a disk switching means that switches and outputs selection signals for the first and second hard disks to be accessed among the hard disks, and among the hard disks, A switch means for arbitrarily switching and setting the hard disk to be the first access target, and a switching means for deriving the selection signal of the hard disk to be the first access target to a control circuit corresponding to the arbitrarily set first access target hard disk, and switching output. a selection signal deriving means for deriving another selection signal obtained by the selection to a control circuit corresponding to a second access target hard disk.