JPH04331471A - Sine wave pwm signal generator - Google Patents

Abstract

PURPOSE:To alleviate the load of software by performing the interrupting processing of output variation timing every N times. CONSTITUTION:An operating means in a CPU 101 generates an interrupting processing at a time point close to the top or bottom point of a triangular carrier and operates the output variation timing of each phase for every interrupting processing of N times based on a sine wave data and the triangular wave carrier. Thus operated output variation timing of each phase is then subjected to output control every time when the interrupting processing occurs. An output control means 107 stores the output variation timing through a timing setting means and a PWM signal for varying the output with the output variation timing is outputted through a port 106. The reference sine wave data is stored in a ROM 104.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention applies to sine wave PWM (Pulse Wide Mod) used in inverters, etc.
ulation) signal generator.

0002

[Prior Art] FIGS. 11 to 15 show, for example,
This shows a conventional sine wave PWM signal generator using a microcomputer as disclosed in Publication No. 3-31477, and FIG.
1, the solid line shows the flow of interrupt processing for PWM signal generation, and the dotted line shows the flow of main processing for creating waveform generation data. 13 and 1 during main processing.
A CPU (102) that performs program control based on the flowchart shown in FIG.
An interrupt request is output to the PU (101), and the above CPU (
Time data is set from 101), and a timer outputs an interrupt request to the CPU (101) based on the time data. Two waveform generation data tables are secured at (103), and the waveform generated by the main processing. A RAM (104) stores generated data, a ROM (105) stores reference sine wave data, etc. for creating waveform generation data to be stored in the RAM (103) during main processing. An address pointer that outputs the waveform generation data address in the waveform generation data table in the RAM (103), (106) is the address pointer for the CP
This port receives port output data from U (101) and generates a PWM signal.

Next, the sine wave PWM constructed in this way
The operation of the signal generator will be explained. First, interrupt processing will be explained based on FIG. 12. Timer (10
When an interrupt request is made from 2) to the CPU (101), the CPU (101) enters a timer interrupt. Then,
As shown in step (121), the address pointer (1
05), and proceeds to step (122), where it is determined whether the waveform generation data table in RAM (103) has reached its end. If it is determined that it has ended, step (
123), if it is determined that it is not the end, step (12
Proceed to 6). In step (123), RAM (103)
It is determined whether or not it is necessary to switch the waveform generation data table in
The waveform generation data table in AM (103) is switched, and if it is not needed, the process proceeds to step (126). Step (
125) initializes the address pointer (105),
In step (126), the waveform generation data in the waveform generation data table of the RAM (103) specified by the address pointer (105) is read into the CPU (101), and outputted to the port (106) as port output data,
A PWM signal is output. Then step (127)
The time data is sent from the CPU (101) to the timer (102).
) and terminates interrupt processing. Thereafter, an interrupt request is made at a timing based on the time data set by the timer (102), interrupt processing is started, and a PWM signal is generated from the port (106).

Next, the process (main process) of storing waveform generation data in the waveform generation data table of the RAM (103) will be explained based on FIGS. 13 and 14. Figure 1
In step (131) in step 3, it is determined whether there is a change in frequency and voltage, and if there is a change, a data creation program is called in step (132). When this data creation program is called, processing is performed based on the flowchart shown in FIG. That is, in step (141), the waveform generation data table in the RAM (103) that is not used by the timer interrupt is selected. Next, in step (142), frequency data, voltage data, carrier frequency data, and ROM (1
04) Create waveform generation data for 30° using the triangular wave comparison method from the reference frequency data stored in the
Proceed to step (143). In step (143), this waveform generation data is developed into 60° worth of data, and in step (144), time-short data that cannot be processed by the microcomputer is cut. When the data creation is completed, a flag indicating that the table can be changed is set in step (145) and the process returns to the main process shown in FIG. This causes the waveform generation data to be rewritten in the waveform generation data table in the RAM (103).

The sine wave PWM signal generator configured as described above operates as described above, and the timing at which timer interrupt processing occurs is as shown by the arrow in FIG. This is the one that caused the interrupt.

FIGS. 16 and 17 are, for example, Japanese Patent Laid-Open No. 61-1
This shows a conventional pulse width modulation inverter control device disclosed in Japanese Patent No. 50671, and in FIG.
1) is a microprocessor, (2) is a memory that stores data related to the time of the PWM pulse pattern, (3) is an I/O port that latches the data stored in this memory, and (4) and (5) are this First and second counters each setting the time data of the PWM pulse pattern latched at the I/O port, the output from the first counter is input as a set signal, and the output from the first counter is input to the second counter. (5) A flip-flop whose output is input as a reset signal; (20) the microprocessor (1), memory (2), I/O port (3), first and second counters (4); (5) and a first pulse forming circuit constituted by a flip-flop (6), (2
1) is a second pulse forming circuit having the same configuration as this first pulse forming circuit, and (7) is a clock signal to be input to the first and second counters (4) and (5). (8) is a frequency divider that divides the output from this oscillator to a desired carrier frequency and outputs a frequency-divided signal;
(9) is an n-bit shift register operated by the frequency division signal from this frequency divider, and (10) and (11) are the first and second pulse forming circuits (20) operated by the output from this n-bit shift register. ) (21) first and second timing signal generation for generating load signals for input to the first and second counters (4) and (5) and interrupt signals for input to the microprocessor (1); circuit,
(12) is the first and second pulse forming circuit (20)
This is an OR circuit that logically adds the outputs from the flip-flop (6) of (21).

Next, the operation of the conventional pulse width modulation inverter control device configured as described above will be explained with reference to the waveform diagram shown in FIG. 17. Data t11, t12, t21, t22, t31 regarding the time from a certain time reference point to the rising and falling points of each pulse
, t32, t41, t42, t51, t52, t61,
t11, t12, t31, t32, t5 of t62
1, t52 is the memory (
2), also t21, t22, t41, t42, t61
, t62 is the memory (2) of the second pulse forming circuit (21).
) is stored in advance. Now, preset the first output C1 from the n-bit shift register (9) to "H" and the second output C2 to "L" between t1 and t2, and The frequency signal B is transferred to an n-bit shift register (
9), its first and second outputs C1 and C
2 is as shown in C1 and C2 in FIG.
5, interrupt signal E1 (load signal D
1) is output, and the microprocessor (1) of the first pulse forming circuit (20) is interrupted by this interrupt signal E1.

Now, for convenience, the first pulse forming circuit (20
) at t3.
1, data t31 is sent to the I/O port (3) after the specific processing time θ of the microprocessor (1) has elapsed from time t1 due to the interrupt signal E1 output at time t1.
The data t32 is then read out from the memory (2), and after the processing time θ has passed, it is latched at the I/O port (3). F1 (t31) and G1 (t32) output from this I/O port (3) are generated when the load signal D1 output from the first timing signal generation circuit (10) at time t3 becomes "H". , are set in the first and second counters (4) and (5), respectively. The first and second counters (4) and (5) start counting down from the fall of the load signal D1 described above using the clock signal A output from the oscillator (7), and when they count time t31, A set signal is applied from the first counter (4) to the S input of the flip-flop (6), and the output Q of the flip-flop (6) becomes "H". On the other hand, when the second counter (5) counts down the time t32, a reset signal is applied from the second counter (5) to the R input of the flip-flop (6), and the output Q of the flip-flop (6) becomes "H". ” to “L”. In other words, the flip-flop (
The output Q of 6) becomes "H", which is shown in H in FIG. 17 (3)
pulses will be output.

By the way, since the next interrupt signal E1 is output from the first timing signal generating circuit (10) at time t3, the processing time θ of the microprocessor (1) of the first pulse forming circuit (20) Data t51 and t52 are sequentially latched to the I/O port (3) at each time. I
Data F1 (t51) and G1 from /O port (3)
(t52) is activated by the load signal D1 from the first timing signal generation circuit (10) output at time t5.
and second counters (4) and (5), and start counting down in the same way as in the above case. As a result, the output Q from the flip-flop (6) is t52−
The period t51 becomes “H”, and (
5) pulse is output. In addition, data t11 and t
12, due to the load signal D1 from the first timing signal generation circuit (10) output at time t1,
During the period t12-t11, the output Q from the flip-flop (6) becomes "H", and the pulse (1) of H shown in FIG. 17 is output.

On the other hand, the second timing signal generation circuit (1
1), the interrupt signal E from the first timing signal generation circuit (10) is output at times t1, t3, and t5.
Time t2, t4, t after a time difference of tc'/2 than 1
An interrupt signal E2 (load signal D2) is output at 6, and this interrupt signal E2 interrupts the microprocessor (1) of the second pulse forming circuit (21). Now, for convenience, let us assume that the beginning of the data read from the memory (2) of the second pulse forming circuit (21) is t41. By the interrupt signal E2 outputted at time t2, data t41 is changed from time t2 to microprocessor (1). ) after the unique processing time θ has elapsed, this data t
41 is latched at the I/O port (3), then data t42 is read from the memory (2), and after the processing time θ has elapsed, this data t42 is latched at the I/O port (3). This I/O port (3) outputs F2 (
t41) and G2 (t42), when the load signal D2 output from the second timing signal generation circuit (11) at time t4 becomes "H", the first and second counters (4)
and (5), respectively.

[0011] First and second counters (4) and (5)
starts counting down from the fall of the load signal D2 described above using the clock signal A output from the oscillator (7), and when the time t41 is counted, the first
A set signal is applied from the counter (4) to the S input of the flip-flop (6), and the output Q of the flip-flop (6) becomes "H". On the other hand, when the second counter (5) counts down the time t42, a reset signal is applied from the second counter (5) to the R input of the flip-flop (6), and the output Q of the flip-flop (6) becomes "H". ” to “L”. In other words, the flip-flop (
The output Q of 6) becomes “H” and is shown in I of FIG. 17 (4)
pulses will be output.

In this way, data t61 and t62
Similarly, for the data t21 and t22, the pulses (6) and (2) of I shown in FIG. 17 are output from the flip-flop (6). 17 from the flip-flop (6) of the first pulse forming circuit (20).
The pulse shown at H in FIG. 17 and the pulse shown at I in FIG. 17 from the flip-flop (6) of the second pulse forming circuit (21) are logically summed by the OR circuit (12), and the pulse shown at J in FIG. A pulse train is output and a pulse width modulated signal is obtained.

[0013]

However, in the conventional sine wave PWM signal generation device shown in FIG. Since output to (106) is also performed by software, it is difficult to obtain output timing accuracy. In addition, although the RAM (103) has two large waveform generation data tables, since the RAM capacity cannot be increased, there are significant restrictions when other programs coexist. Furthermore, although it is possible to change the voltage and frequency at intervals of 20 ms in the case of the output frequency cycle, for example 50 Hz, it cannot be used in applications where the frequency and voltage need to be changed over hundreds of microseconds, such as motor vector control. It is.

Furthermore, the conventional control device for the pulse width modulation inverter device shown in FIG. 16 requires a plurality of, at least two, microprocessors (1) to create one pulse train. The structure of the wear was complicated and the cost was high.

The present invention has been made in view of the above-mentioned points, and eliminates the need to provide a waveform generation data table in the RAM, simplifying the configuration, and reducing the need for a single microprocessor.
The object of the present invention is to obtain a sine wave PWM signal generator which can be realized by using the following method and which can also change the output voltage and frequency every N/2 carrier frequency.

[0016]

[Means for Solving the Problems] A sine wave PWM signal generation device according to the present invention generates an interrupt process at at least one of a time point in the vicinity of the highest point of a triangular wave carrier or a time point in the vicinity of a triangular wave carrier including the lowest point. and N times (N
is an integer greater than or equal to 2); and a calculation means for calculating the output change timing of each phase for each interrupt processing; and a timing for output control of the output change timing of each phase obtained by the calculation means each time an interrupt processing occurs. The device is provided with a setting means and an output control means for storing the output change timing set by the timing setting means and outputting a PWM signal for changing the output at the stored output change timing. .

[0017]

[Operation] In this invention, the arithmetic means generates an interrupt process at at least one of the points in the vicinity of the top point of the triangular wave carrier or the points in the vicinity of the bottom point of the triangular wave carrier, N times (N is 2 or more). The output change timing of each phase is calculated for each interrupt processing (an integer), and the timing setting means sets the output change timing of each phase obtained by the calculation means to the output control means every time an interrupt processing occurs, and the PWM This is what outputs the signal.

[0018]

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 and 1.
The explanation will be based on 0. In FIG. 1, (101) performs program control based on the flowcharts shown in FIGS. 3 to 5 during interrupt processing, and performs program control based on the flowcharts shown in FIGS.
C that performs program control based on the flowchart shown in
As shown in FIG. 2, the PU performs interrupt processing at at least one of the points near the top of the triangular wave carrier (201) or the bottom of the triangular wave carrier (201) (in both cases in FIG. 2). (Indicated by arrow in Figure 2)
is generated, and the output change timing of each phase, that is, the sine wave data and the triangular wave carrier (201) are compared every N times (N is an integer of 2 or more) to determine whether the switching element of each phase is turned on or off. It has the functions of a calculation means for calculating timing, and a timing setting means for controlling the output change timing of each phase determined by the calculation means every time an interrupt process occurs.

(102) is a timer, and (103a) is voltage multiplication data necessary for calculating the output change timing, that is, output voltage data that is preset in a V/F pattern with respect to the actual output voltage and the output frequency. A first RAM (103b) that stores data that is a coefficient when determining from standard output voltage data, which is a standard output voltage data, constitutes a storage means that temporarily stores the output change timing determined by the calculation means of the CPU (101). Second RAM, (104)
stores the reference sine wave data that is the standard for creating sine wave data in the triangular wave comparison method that compares the sine wave data and the triangular wave carrier (201) to obtain the output change timing of each phase, the standard output voltage data, etc. ROM
, (105) is an address pointer indicating an address for accessing the reference sine wave data stored in this ROM (104), (106) is a port that outputs a PWM signal,
(107) has a register (108) that stores the output change timing and interrupt timing set by the timing setting means of the CPU (101), and changes the output at the output change timing stored in this register (108). Output control means (109) is an I/O unit that inputs and outputs information to and from external devices, sensors, and the like.

Next, the operation of the sine wave PWM signal generator constructed in this manner will be explained. First, interrupt processing will be explained based on FIG. 3. First, step (
301), the ROM indicated by the address pointer (105)
The reference sine wave data is sent from the address of (104) to the CPU (
101) is read. The reference sine wave data read in step (302) is stored in the ROM (104), and is stored in the first RAM (103a) by main processing.
The standard output voltage data transferred to the first RAM (1
03a), and based on this multiplication result and the triangular wave carrier (201), calculate the output change timing during the rise of the triangular wave carrier (201) between interrupt timings. The calculation result is stored in the second RAM (103b) in step (303).
). Next, in step (304), in order to calculate the output change timing during the descent of the triangular carrier (201), the carrier period of the triangular carrier (201) is calculated from the output change timing data obtained in step (302). is subtracted, and the subtraction result is stored in the second RAM (103b) in step (305). Next, in order to calculate the output change timing of other phases, step (
At step 302), the address pointer (105) is advanced by a value corresponding to the phase difference, and at step (307), the reference sine wave data stored in the ROM (104) indicated by this address pointer (105) is read.

[0021] Then, in step (308), the read reference sine wave data is stored in the first RAM (103a).
) and the standard output voltage data stored in the first RAM.
(103a) is multiplied by the voltage magnification data stored in
Based on this multiplication result and the triangular wave carrier (201),
Triangular wave carrier (201
) is calculated, and the calculation result is stored in the second RAM (10) in step (309).
3b). Next, in step (310), in order to calculate the output change timing during the descent of the triangular carrier (201), the carrier period of the triangular carrier (201) is calculated from the output change timing data obtained in step (308). is subtracted, and this subtraction result is used in step (311
) in the second RAM (103b). Through the above steps, all timings within the triangular wave carrier (201) are determined. Next, in step (312), the address of the address pointer (105) is advanced by an amount corresponding to the output frequency, and in step (313), it is determined whether the address in the address pointer (105) exceeds the range of the table. death,
If it exceeds, the process advances to step (314) and the address pointer (105) is initialized. In this way, the output change timing of each phase is determined for each interrupt process.

On the other hand, the timing setting means in the CPU (101) operates based on the flowchart shown in FIG. First, in step (401), the triangular wave carrier (
201) determines whether to set the timing while ascending or descending, and if it is ascending, the step (402) is set, and if it is descending, the step (40) is set.
Proceed to 4). In step (402), the operation step (
The output change timing stored in step (303) is set in the register (108) of the output control means (107), and in step (403) the operation step (309) in the calculation means of the CPU (101) shown in FIG. ) is set in the register (108) of the output control means (107). Similarly, when descending, steps (404) and (405) output the output change timing stored in steps (305) and (311) of the operation in the calculation means of the CPU (101) shown in FIG. Set in the register (108) of the control means (107). In this way, the output change timing of each phase determined for each interrupt process by the arithmetic means of the CPU (101) can be set in the register (108) of the output control means by the timing setting means.

Next, how the processing of the arithmetic means and timing setting means of the CPU (101) described above is executed within the interrupt processing will be explained using FIG. First, when an interrupt request occurs and interrupt processing begins, an interrupt processing counter (not shown) is set in step (501).
is incremented, and the process branches at step (502) according to the value of the counter. If the count value of the counter is 1, the process proceeds to step (503), where the processing by the calculation means of the CPU (101), that is, the process based on the flowchart shown in FIG. 3, is performed, and the process proceeds to step (505). Also, if the counter values are 2 and 3 in step (502), the process proceeds to step (505), and if the count value is 4, the counter value is set to 1 in step (504), and step (505) is performed. Proceed to. In step (505), the processing of the timing setting means of the CPU (101), that is, the processing based on the flowchart shown in FIG. 4, is performed, and the interrupt processing is ended.

The order in which these processes are executed is shown in FIG. 6 in terms of timing. In other words, the first
When the second interrupt generation timing occurs, the processing of the calculation means - the processing of the timing setting means - the main processing - the generation of the second interrupt generation timing - the processing of the timing setting means - the main processing - the generation of the third interrupt generation timing - Processing of timing setting means - Main processing - 4
This is performed as follows: generation of the first interrupt generation timing - processing of the timing setting means - main processing - generation of the first interrupt generation timing - processing of the calculation means.
The calculation of the output change timing is performed every N times, or every 4 times in this embodiment, and each time the output change timing data stored in the second RAM (103b), which is a storage means, is set.

Then, as described above, the calculation means and timing setting means of the CPU (101) perform calculations for interrupt processing, and the output change timing is set in the register (108) of the output control means (107). Then, the output control means (107) transmits the output change timing data stored in the register (108) to the timer (10
2), and when the two match, the output is output to the port (106) to output a PWM signal, and an interrupt request is generated to the CPU (101).

Next, the main processing will be explained based on FIG. This main processing is a process of importing external conditions and data through the I/O (109) and calculating data regarding the output frequency and output voltage. Data is captured, and in step (702) the output frequency and voltage magnification are calculated from the captured conditions and data. Then, from the output frequency determined in step (703), the standard output voltage and address pointer (1
05) is read out from the ROM (104) or calculated and stored in the first RAM (103a).

[0027] In the above embodiment, the CPU (101
), the output change timing is calculated based on the multiplication of the reference sine wave data, standard output voltage data, and voltage multiplication data according to the flowchart shown in Figure 3, but specifically, it is calculated as follows. It is something that In other words, the standard output voltage data is treated as 8 bits, the voltage magnification data as 8 bits, and the reference sine wave data as 9 bits, and when these are multiplied, it becomes 24 bits (or more) of data, and then the 24 bits (or more) The lower 16 bits of data are rounded down to 8 bits (or more) of data, and the size of each value is adjusted so that it becomes the value set in the timer that determines the output change timing inside the microprocessor. It adjusts the

In addition, the output change timing during the falling triangular wave carrier is symmetrical as shown in FIG. It can be found by subtracting the data time a of the output change timing.

Furthermore, the data stored in the ROM (104) is as follows. In other words, when holding reference sine wave data in 8 bits, generally, as shown in Fig. 9, 0 is stored when SinX is 0, 255 is stored when SinX is 1, and 1/2 to 1 are stored. , the value ranges from 128 to 255, and in reality only a 7-bit resolution can be obtained, but in the above example, as shown in FIG. 10, SinX is 1/2
0 when SinX is 1, and 255 when Sin
The bit is always set to 1 and is used as 9-bit data, so even if it is stored in ROM (104) as 8-bit data, it is obtained as 9-bit data. It is something that exists.

In the above embodiment, the interrupt processing is assumed to occur twice in one carrier period of the triangular wave carrier, but the interrupt is generated only at one of the timings, and when the triangular wave carrier is rising and falling. The timing setting process, which was previously performed separately, may be performed at once. Also, it is assumed that the output change timing is calculated every four interrupts, but N times (
The calculation may be performed for each interrupt (N is an integer of 2 or more).

[0031]

Effects of the Invention As described above, the present invention generates an interrupt process at at least one of the points in the neighborhood including the top point of the triangular carrier or the points in the neighborhood including the bottom point, and interrupts N times ( calculation means for calculating the output change timing of each phase obtained based on the sine wave data and the triangular wave carrier for each interrupt processing (N is an integer of 2 or more);
A timing setting means for output-controlling the output change timing of each phase obtained by the calculation means every time an interrupt process occurs, and a timing setting means for storing the output change timing controlled by the timing setting means, and storing the output change timing. Since the output controller is provided with an output control means for outputting a PWM signal for changing the output, the number of interrupt processing is reduced, in other words, the calculation processing of the output change timing is only performed once every N times, and the software This has the effect of reducing the burden on the wearer.

Further, the output voltage and the output frequency can be changed independently every N/2 carrier period, and the frequency of the triangular wave carrier can be increased. Furthermore, in order to determine the output change timing, it is only necessary to have reference sine wave data and standard output voltage data in the ROM.
Moreover, since the RAM constituting the storage means does not need to have a table unlike the conventional example shown in FIG. 11, the RAM capacity can be reduced. Furthermore, if the output voltage is obtained by varying the voltage multiplier based on the standard output voltage data, the control mechanism of the controlled device that is operated by changing the output voltage using some kind of feedback control can be guaranteed. Even if a failure occurs, emergency operation can be performed using a preset V/F pattern.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing the timing of interrupt processing in the sine wave PWM signal generator shown in FIG. 1;

FIG. 3 is a flowchart for calculating the output change timing of interrupt processing in the sine wave PWM signal generator shown in FIG. 1;

FIG. 4 is a flowchart for setting the timing of interrupt processing in the sine wave PWM signal generator shown in FIG. 1;

FIG. 5 is a flowchart showing interrupt processing in the sine wave PWM signal generator shown in FIG. 1;

FIG. 6 is a timing chart showing the order in which interrupt processing is executed in the sine wave PWM signal generator shown in FIG. 1;

FIG. 7 is a flowchart showing main processing in the sine wave PWM signal generator shown in FIG. 1;

FIG. 8 is a diagram for explaining a calculation method for output change timing in the sine wave PWM signal generator shown in FIG. 1;

FIG. 9 is a diagram showing how to hold general reference sine wave data.

FIG. 10 is a diagram showing how reference sine wave data is held in the sine wave PWM signal generator shown in FIG. 1;

FIG. 11 is a block diagram showing a conventional sine wave PWM signal generator.

FIG. 12 is a flowchart showing interrupt processing in the sine wave PWM signal generator shown in FIG. 11;

FIG. 13 is a flowchart showing main processing in the sine wave PWM signal generator shown in FIG. 11;

FIG. 14 is a flowchart showing a data creation program in the sine wave PWM signal generator shown in FIG. 11;

FIG. 15 is a diagram showing the timing of occurrence of interrupt processing in the sine wave PWM signal generator shown in FIG. 11;

FIG. 16 is a block diagram showing a conventional pulse width modulation inverter control device.

FIG. 17 is a diagram showing the timing of occurrence of interrupt processing in the control device for the pulse width modulation inverter shown in FIG. 17;

[Explanation of symbols]

101 CPU having functions of calculation means and timing setting means 103b RAM 107 constituting storage means
Output control means 201 Triangular wave carrier

Claims (1)

[Claims] Claim 1: An interrupt process is generated at at least one of a time point near the top point of the triangular wave carrier or a time point near the bottom point, and every N times (N is an integer of 2 or more). a calculation means for calculating the output change timing of each phase obtained based on the sine wave data and the triangular wave carrier, and output control of the output change timing of each phase obtained by this calculation means every time an interrupt process occurs. a sine wave PWM signal output comprising a timing setting means for controlling the output, and an output control means for storing the output change timing controlled by the timing setting means and outputting a PWM signal for changing the output at this output change timing. Device.