JPH04332231A - Clock regerating system - Google Patents

Abstract

PURPOSE:To correctly regenerate a clock from received data having different duty ratio by controlling a phase correcting amount greater than twice of the deviation of the duty ratio of input signal when the phase difference is greater than a constant phase angle. CONSTITUTION:Phase difference theta between an input signal Fi and feedback signal Ff is detected by a phase error range detecting circuit 31, and when the phase difference is greater than a constant phase angle thetac (20 deg.<thetac<90 deg.), control is made so that when phase control amount alpha of oscillating circuit 50 for one time phase detecting is greater than 2delta. Here, delta is the deviation for dutilization of input signal Fi. Thus, when deviation delta of duty ratio in input signal Fi is present, a clock can be regenerated without causing deadrock. Further, when the phase difference theta between input signal Fi and feedback signal Fh is smaller than constant phase angle thetac, by controlling the phase control amount a to be much smaller, a phase jitter can be made small and the degradation of performance can be protected.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a clock recovery method using a digital phase-locked loop (hereinafter abbreviated as DPLL), and in particular, there is a difference in the duration of 1 and 0, resulting in a difference in duty. This invention relates to a method for correctly regenerating a clock at high speed from received data with different ratios.

0002

[Prior Art] A digital PLL that reproduces a clock from received data at high speed and has excellent operating characteristics in steady state.
An example of the device is disclosed in Japanese Patent Laid-Open No. 61-265922.

FIG. 1 is a schematic diagram of the digital PLL device. In FIG. 1, 11 is an input terminal to which an input signal Fi is applied, 12 is an output terminal to which a feedback signal Ff is output, and 13 is a terminal to which a master clock signal MCP is input. 30 is a phase detector that detects the phase difference between the input signal Fi and the feedback signal Ff, and 31 is a phase error range detector that detects the range of phase error between the input signal Fi and the feedback signal Ff. The output of this phase error range detection circuit 31 passes through a speed control circuit 32 to control a low pass filter 40 and a reset control circuit 33. The low-pass filter 40 includes a counter, a decoder, etc., and integrates the output of the phase detection circuit 30, and outputs a signal CS2 to the reset hold circuit 34 when a predetermined count value (assumed M) is reached. Oscillation circuit (VCO) 5
0 is an oscillation circuit consisting of a programmable counter, etc., and it regularly inputs the master clock signal MCP and sends it to n.
The frequency is divided and an oscillation signal Fo is output.

Here, if the phase detection circuit 30 detects a phase lag and the integrated value of the low-pass filter 40 reaches a predetermined count value, the reset hold circuit 3
4 determines that the current phase is delayed, and sets the frequency division number of the oscillation circuit 50 to (n-l) in order to increase the oscillation frequency. Here, l is a preset value. Conversely, when the phase detection circuit detects a phase advance, the reset hold circuit 34 determines that the current phase is advanced, and divides the frequency division number of the oscillation circuit 50 by (n+l) in order to lower the oscillation frequency. Make it. When a programmable counter is used as the oscillation circuit 50, the reset data of the programmable counter is successively changed under the control of the reset hold circuit 34.

The reset control circuit 33 is the speed control circuit 32
This is a circuit that varies the amount of phase correction performed in the oscillation circuit 50 based on the control signal CS1 of the oscillation circuit 50.
Controls how many times the (n-l) or (n+l) frequency division is performed. When the number of phase corrections of the oscillation circuit 50 reaches a preset number of times (J times), the reset control circuit 33 gives a command signal CS4 to end the phase correction to the reset hold circuit 34, and ends the phase correction operation. let At the same time, the reset hold circuit 34
receiving the command signal CS4 and outputting the reset signal CS3;
Reset the counter of low pass filter 40.

The frequency divider 60 is a fixed frequency dividing circuit, which divides the frequency of the oscillation signal Fo from the oscillation circuit 50 by N, and outputs this as a feedback signal Ff to the output terminal 12, the phase detection circuit 30, and the phase error range detection circuit 31. give to The phase error range detection circuit 31 is composed of a phase change circuit composed of a shift register, etc., and two phase detection circuits.
For example, whether it is within ±60° or more than that.

The reset hold circuit 34 is a low-pass filter 4
The output signal CS2 of 0 is latched and its output is given to the oscillation circuit 50 as a control signal to control the oscillation frequency of the oscillation circuit 50. When the command signal CS4 output from the reset control circuit 33 is input to the reset hold circuit 34 as a reset signal, the reset hold circuit 34 releases the control of the oscillation circuit 50 and sets the frequency division ratio of the oscillation circuit 50 to n. Return to.

Here, for example, the feedback signal Ff
If there is a phase lag of 120°, the phase detection circuit 30 determines that there is a phase lag, and the low-pass filter 40 integrates its output. On the other hand, the phase error range detection circuit 31 determines that there is a large phase lag (for example, exceeding 60°), and the integrator circuit M of the low-pass filter 40 is changed to 1 through the speed control circuit 32.
(one example), and J of the reset control circuit 33 is set to 30 (
example). Therefore, information on the phase delay is immediately transmitted to the reset hold circuit 34, and the frequency division ratio of the oscillation circuit 50 is held at (n-l). Further, since a large value J=30 is set in the reset control circuit 33, the frequency division ratio (n-l) of the oscillation circuit 50 is repeated 30 times, and high-speed phase correction is performed. When the phase correction progresses and the phase error becomes, for example, within 60°,
The phase error range detection circuit 31 detects that the phase error has become within 60°, sets the number of integrations M=2 (an example) of the low-pass filter 40 through the speed control circuit 32, and also sets the number of integrations M=2 (one example) to the reset control circuit 33 Set J=10 (one example). Therefore, even if the phase detector 30 detects a phase lag, the low-pass filter 40 counts twice before transmitting the signal CS2 to the reset hold circuit 34. Further, the frequency division ratio (n-l) of the oscillation circuit 50 is set to J=10 by the reset control circuit 33.
Since this small value is set, it will be repeated 10 times, so the phase correction will be slight, and the phase correction speed will be slow, resulting in a feedback signal F with less jitter.
f can be obtained. That is, when the phase error is large, phase correction is performed at a high speed, and when the phase error becomes small, the phase correction speed is slowed down to reproduce a clock with less jitter.

[0009]

[Problems to be Solved by the Invention] However, in the clock regeneration method described above, in the case of input signals with different duty ratios of 1 and 0, the phase of the feedback signal Ff cannot follow the phase of the input signal Fi. There was a drawback that there was. This probability is 1 in 100 or 10
Although the probability is small, such as 2 out of 0 times, even such a small probability becomes a big problem in order to ensure reliable communication.

This phenomenon will be explained below using FIG. As shown in FIG. 2(1), it is assumed that the duty ratios of 1, 0, . . . of the input signal Fi are different, and the deviation of the duty ratios is δ. In this case, the phase of the reproduced clock Ff is largely shifted from the phase of the input signal Fi as shown in FIG. 2(3), and when the phase shift is approximately 180°,
As shown in 4), phase determination is performed alternately with delay, advance, delay, and advance. Therefore, as shown in FIG. 2 (5), the phase correction is performed alternately by advancing, delaying, advancing, and delaying, and the reproduced clock Ff never reaches the correct phase (hereinafter, this phenomenon is referred to as deadlock).
.

FIG. 6 shows an example of actually measured values of burst signal reception characteristics, and the dotted line indicates the above phenomenon. This burst signal reception characteristic was measured as follows. In other words, since it is quite difficult to define and judge at what point the phase of the reproduced clock reaches the correct value, a 15-bit frame period signal is generated after the preamble (18 consecutive bits of 1, 0, 1, 0...). We decided to send burst-shaped data with a . The clock phase on the sending side was changed randomly each time, so that there was no influence from the phase of the burst signal sent immediately before. The dotted line in FIG. 6 indicates that when the duty ratio deviation δ is approximately 6°, reception was not possible at a rate of about 1/100 to 3/100 even if the S/N ratio was improved.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a clock regeneration method that solves the above-mentioned problems and can reliably regenerate a clock without causing deadlock in any case.

[0013]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a phase detection circuit that detects whether or not an input signal is ahead in phase with respect to a feedback signal and outputs a detection signal thereof; a low-pass filter that integrates a signal, attenuates high-frequency components, and outputs a filtered signal; an oscillation circuit that corrects the phase of the filtered signal and outputs an oscillation signal of a predetermined frequency; a frequency divider that divides the frequency by a ratio and outputs the feedback signal, and in a clock regeneration method that regenerates a clock from the input signal, a first circuit that detects a phase difference between the input signal and the feedback signal; , a second circuit that controls the amount of phase correction of the oscillation circuit based on the phase difference, and the phase difference has a constant phase angle θc (however, 20°<θc<9
0°), the phase correction amount is controlled to be larger than twice the deviation of the duty ratio of the input signal.

[0014]

[Operation] When the phase difference between the input signal and the feedback signal is larger than a constant phase angle θc (however, 20°<θc<90°), the phase control amount α of the oscillation circuit for one phase detection is The duty ratio deviation δ is controlled so as to satisfy the relationship α>2δ. This allows the clock to be regenerated without deadlock even when the input signal has a duty ratio deviation δ. Further, when the phase difference between the input signal and the feedback signal is smaller than the constant phase angle θc, the phase control amount α is controlled to be smaller. This makes it possible to reduce the phase jitter and prevent performance deterioration.

[0015]

Embodiment First, a description will be given of how phase correction is performed in a DPLL for clock recovery.

FIG. 3 is a diagram illustrating the phase correction operation when the duty ratio deviation δ of the input signal Fi is zero. In FIG. 3, (1) indicates a preamble portion of received data (input signal Fi). This preamble portion is composed of continuous signals of 1, 0, 1, 0, etc. that contain the most phase information. In (2), the changing points of the input signal Fi are extracted in order to obtain phase information. (3) is the regenerated clock (feedback signal Ff), and in this figure, the phase was initially delayed from the input signal Fi, so
Phase determination as shown in (4) is performed, phase correction is performed at the temporal timing as shown in (5), and eventually the input signal Fi shown in (1) and the recovered clock (feedback signal Ff) comes to match in phase.

However, in general, the phase determination circuit shown in FIG.
As shown in the figure, the phase determination result has the property of being reversed at ±180°. That is, a phase delay exceeding 180° is determined to be a phase lead, and a phase lead exceeding 180° is determined to be a phase lag. Therefore, if input signals with different duty ratios are input, and the phase difference between the input signal and the reproduced clock is close to 180°, a deadlock may occur and the phase may not be corrected.

FIG. 2 is a diagram illustrating a phase correction operation when there is a duty ratio deviation δ in the input signal Fi and the phase between the input signal Fi and the reproduced clock is close to 180°. In Figure 2, (1) to (5) correspond to (1) to (5) in Figure 3.
5), and the received data (input signal Fi) is shown in Figure 3.
As in (1), it is a series of 1, 0, 1, 0..., but the duty ratio is different and there is a deviation δ as shown in the figure. Regenerated clock (3) (feedback signal Ff) is
The correct phase is the rising edge at the change point (2) of the input signal, but since there is a duty ratio deviation δ, each time the phase is determined, it lags, advances, lags, advances...
It is determined that the phase correction (5) is also advanced, delayed, advanced, delayed, etc., and the phase is never correct, resulting in a deadlock. This will be explained in detail below using a different expression to make it easier to understand.

FIGS. 4(a) to 4(c) express the relationship between the phase of the input signal and the phase of the reproduced clock, as well as phase determination and phase control. Here, the horizontal axis indicates the passage of time, odd numbers indicate phase determination timing, and even numbers indicate phase control timing. The vertical axis shows the phase, the dotted line shows the correct phase of the input signal, the solid line shows the phase of the recovered clock, and the +δ and -δ arrows are recognized as different from the correct phase because the input signal duty ratio is different. The tip of the arrow indicates the recognized phase. Note that the phase of the reproduced clock is expressed as being shifted by 180° from the phase of the input signal. This is because the above-mentioned deadlock occurs when the input signal and the reproduced clock are out of phase by approximately 180°, and it is easier to understand if they are expressed as if they are shifted by 180° and overlap. In addition, as mentioned above, the phase determination circuit reversely determines whether the phase is advanced or delayed with 180 degrees as the boundary, so the direction of phase correction is as shown in FIGS. It is easy to understand because it is only necessary to recognize that the direction in which the phases of the and reproduced clocks move away from each other is the direction of correct phase control. Based on this assumption, Figures 4(a) to (
c) will be explained in order.

FIG. 4(a) shows that the initial phase of the recovered clock is 1.
This is an example where the phase control does not converge because the angle is 80°. In the figure, since it is determined that the phase of the input signal is advanced at timing number 1 (hereinafter referred to as timing 1), the reproduced clock is controlled to be delayed by α at timing 2. Since it is determined at timing 3 that the phase of the input signal is delayed, at timing 4 the reproduced clock is controlled to advance by α. Since it is controlled to delay, advance, delay, advance... in this way, it is difficult to control the phase to the correct phase (as described above, Figs. 4(a) to (c)
), the correct phase control is to move away from the dotted line in the figure).

Next, FIG. 4(b) will be explained. this is,
This is an example in which the phase control converges because the initial phase of the recovered clock was slightly deviated from 180°. In the figure, since it is determined at timing 1 that the phase of the input signal is advanced, at timing 2 the reproduced clock is controlled to be delayed by α. The process up to this point is the same as in FIG. 4(a). Next, at timing 3, it is determined that the phase of the input signal is leading, so at timing 4, the reproduced clock is controlled to be delayed by α, and in this drawing, it moves away from the dotted line. This means that it receives correct control and converges to the correct phase. Figure 4(a) and (b)
The difference is whether there is a timing at which the phase of the recovered clock jumps outside the ±δ arrows in the diagram. That is, at timing 3 in FIG. 4(b), the phase control was able to converge because the phase of the recovered clock was outside the -δ arrow. This is because the initial phase of the reproduced clock in FIG. 4(b) happened to meet the conditions.

Therefore, considering that this condition holds for any initial phase, considering it diagrammatically in FIG. 4(b), α>2δ
If (1), the phase of the recovered clock must be ±δ
There is a timing when it jumps out of the arrow. This situation is shown in FIG. 4C, which shows that no matter what the initial phase is, the phase of the reproduced clock jumps outside the ±δ arrow in the drawing and converges to the correct phase.

The significance of the present invention lies in the discovery of the condition of formula (1).

The solid line in FIG. 6 shows the actual measurement results of the burst signal reception characteristics when the condition of equation (1) is applied to the DPLL for clock recovery. As shown by this solid line, as the S/N increases, the burst signal non-reception rate decreases, and the S/N
There is no problem at 20 dB or more.

Note that the condition in equation (1) has the same meaning as increasing the phase jitter of the recovered clock, so if left as is, the performance when receiving digital data will deteriorate. However, to deal with this, the method disclosed in Japanese Patent Application Laid-open No. 61-265922 is used to reduce the phase correction angle when the phase error between the input signal and the reproduced clock becomes less than a certain value. As a result, a clock recovery DPLL can be configured without deteriorating performance.

[0026]

As described in detail above, according to the present invention, the amount of phase correction α made at one time can be changed to α>2δ(δ
is the deviation of the duty ratio of the input signal), it is possible to perform correct phase correction control no matter what the initial phase of the recovered clock is, and it is possible to realize a high-speed, high-performance clock recovery DPLL.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a digital PLL device.

FIG. 2 is an explanatory diagram of a phase correction operation.

FIG. 3 is an explanatory diagram of a phase correction operation.

FIG. 4 is an explanatory diagram of a phase correction operation.

FIG. 5 is a characteristic diagram of the phase determination circuit.

FIG. 6 is a diagram showing burst signal reception characteristics.

[Explanation of symbols]

30 Phase detection circuit 31 Phase error range detection circuit 32 Speed control circuit 33 Reset control circuit 34 Reset hold circuit 40 Low-pass filter 50 Oscillation circuit 60 Frequency divider

Claims (1)

[Claims] 1. A phase detection circuit that detects whether an input signal is ahead in phase with respect to a feedback signal and outputs a detection signal thereof; and a phase detection circuit that integrates the detection signal to attenuate high frequency components and output a filtered signal. a low-pass filter; an oscillation circuit that corrects the phase using the filtered signal and outputs an oscillation signal of a predetermined frequency; and a frequency divider that divides the frequency of the oscillation signal at a fixed ratio and outputs the feedback signal. A clock regeneration method for regenerating a clock from the input signal, comprising: a first circuit for detecting a phase difference between the input signal and the feedback signal; and controlling an amount of phase correction of the oscillation circuit based on the phase difference. A second circuit is provided in which the phase difference is a constant phase angle θc (however, 20°<θc
<90°), the amount of phase correction is controlled to be larger than twice the deviation of the duty ratio of the input signal.