JPH04333251A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To reduce the number of processes and time for the cutoff operation and the mounting operation of a chip in a package and package cost by arranging wiring for bias voltage impression in the peripheral part outside the chip. CONSTITUTION:External connection pads 1a and 1b used for the connection of a chip 4 to the outside are provided to bias applying wirings 2a and 2b lccated outside the chip 4, where the bias applying wirings 2a and 2b are provided surrounding the chips 4 on a wafer 5 and connected to the corresponding bias applying pads 3a and 3b of each of the chips 4. Therefore, when a bias is applied to one of the chips 4 from outside in the wafer 5, all the chips 4 can be biased. By this setup, not only the cutoff and the mounting operation of a chip in a package can be lessened in number of processes and time but also the package cost can be lessened.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor wafers.
Especially regarding chip layout on a wafer.

0002

2. Description of the Related Art Conventionally, as shown in FIG. 3(a), the layout of a chip area on a semiconductor wafer has been such that no wiring is provided outside the chip area (referred to as a chip) 4, and the chip 4 is arranged vertically. It was placed to the side. All the chips 4 are arranged on the wafer 5 in an independent state without electrical or physical interaction, and no consideration is given to life tests by applying bias after manufacturing.

Next, a method for testing the life of this chip 4 will be explained. In the life test of the chip 4, all the chips 4 are separated, the chip is assembled in a package, a bias is applied in the packaged state, and the chip is placed in a high or low temperature state to check for accelerated life such as performance deterioration of the chip.

0004

[Problem to be Solved by the Invention] With conventional semiconductor wafers, in order to perform a chip life test, it was necessary to separate the chips and incorporate them into a package.
There are problems in that it takes a considerable amount of time to incorporate into a package, and the package itself is expensive.

Furthermore, in order to test the chip 4 without separating it, a probe card 6 shown in FIGS. 3(b) and 3(c) is required, and the probe 7 for bias application can only be set up on the external chip. The drawback is that it cannot be done. or,
Even if a method of connecting the bias application wiring to the outside with a bonding wire was adopted, the length of the bonding wire would be too long, making it impossible to implement.

[0006]

[Means for Solving the Problems] A semiconductor wafer of the present invention is a semiconductor wafer having a plurality of semiconductor element formation regions, in which DC bias application wiring is provided near at least two sides of the outer periphery of the element formation region. It is configured.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIGS. 1(a) and 1(b) are a schematic diagram of a chip arrangement on a wafer and an enlarged plan view of part A of a first embodiment of the present invention, respectively. A pair of bias application wirings 2a, 2b are provided around the chip 4 arranged on the wafer 5, and the bias application wirings 2a, 2b are connected to the corresponding bias application pads 3a, 3b in the chip. are doing.

External connection pads 1a and 1b are arranged on the outside of the chip for connecting the bias application wiring 2a and 2b with the outside, and a pair of pads 1a and 1b are arranged on the outside of the chip on the wafer 5 around where the chip 4 is placed. Bias application wirings 2a and 2b are provided, and are connected to bias application pads 3a and 3b in the corresponding chips, respectively.

External connection pads 1a and 1b for connecting the bias application wiring lines 2a and 2b with the outside are arranged outside the chip, and are also provided on the periphery of the wafer 5.

FIG. 2 is an enlarged schematic diagram of a chip according to a second embodiment of the present invention.

Bias application wiring lines 2a, 2b and bias application pads 3a, 3b within the chip are directly connected by bonding wires 8. This is advantageous when the positions of the intra-chip pads 3a, 3b vary depending on the chip 4, and it is difficult to connect them directly to the bias application wirings 2a, 2b.

0012

Effects of the Invention As explained above, the present invention enables bias application to be applied to all chips on the wafer by arranging the wiring for bias application in the peripheral area outside the chip, and by connecting each chip from the outside in the wafer state. Since the voltage can be applied, it is possible to shorten the man-hours required for separating the chip and assembling the chip into the package, and to reduce the packaging cost.

[Brief explanation of drawings]

FIGS. 1A and 1B are a schematic diagram of a chip arrangement on a wafer and an enlarged plan view of part A, respectively, of a first embodiment of the present invention.

FIG. 2 is an enlarged plan view of a chip according to a second embodiment of the present invention.

FIGS. 3A to 3C are a schematic diagram of a chip arrangement, a plan view, and a side view of a probe card, respectively, of an example of a conventional semiconductor wafer;

[Explanation of symbols]

1a, 1b External connection pad 2a, 2b Bias application wiring 3a, 3b Pad inside chip 4 Chip 5 Wafer 6 Bonding wire 7 Bias power supply connection pad

Claims (1)

[Claims] 1. A semiconductor wafer having a plurality of semiconductor element formation regions, characterized in that DC bias application wiring is provided near at least two sides of the outer periphery of the element formation region.