JPH04334111A - Digital parametic equalizer circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalizer device used for sound effects, sound quality adjustment, etc.

0002

2. Description of the Related Art FIG. 3 shows the configuration of a conventional digital equalizer circuit. In FIG. 3, 41 is an input terminal, 42, 48, 49, 52, and 53 are multipliers, 43 is an adder, 45 is an output terminal, 46, 47, 50, and 51 are delay devices, and the input terminal 41 is Delay device 46 and multiplier 4 in parallel
2 is entered. The delay device 46 provides a delay of one sampling period. Multiplier 42 performs multiplication with corollary b0. The output of multiplier 42 is connected to one input of adder 43. The output of the adder 43 is connected to an output terminal 45 and a delay device 47 in parallel. delay device 47
The output is connected to a multiplier 49 and a delay device 51 in parallel. Multiplier 49 performs multiplication with series a1. The output of multiplier 49 is connected to one input of adder 43. The output of the delay device 51 is connected to the multiplier 53. Multiplier 53 performs multiplication with series a2. The output of multiplier 53 is connected to one input of adder 43. The output of delay device 46 is connected to multiplier 48 and delay device 50 in parallel. The multiplier 48 performs multiplication with the series b1. The output of multiplier 48 is connected to one input of adder 43. The delay device 50 output is connected to a multiplier 52. The multiplier 52 performs multiplication with the corollary b2. The output of multiplier 52 is connected to one input of adder 43.

Next, the operation of the above conventional example will be explained. According to the configuration shown in FIG. 3, a transfer function expressed by Equation 1 can be obtained. On the other hand, the general formula for the transfer function of an analog second-order filter is shown by the equation 2, and various analog filters can be constructed.By replacing this with the bilinear conversion equation shown in the equation 3, the analog configurable shelving
Various filter configurations such as high, shelving/low, and peaking filters can be configured by digital signal processing.

0004

[Math 1]

[0005]

[Math 2]

[0006]

[Math 3]

[0007]

[Problem to be Solved by the Invention] However, in the conventional signal equalizer described above, the series of each multiplier is determined when performing bilinear transformation, but this series is uniquely determined by the filter type and frequency characteristics. Therefore, even when configuring a vertically symmetrical filter as shown in FIG. 4, there is a problem in that it is necessary to give a coefficient to each filter. The present invention is intended to solve such conventional problems, and it is an object of the present invention to provide an equalizer circuit that can reduce the amount of coefficients by about half when constructing a vertically symmetrical filter.

[0008]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first method that includes an input terminal, a multiplier, an adder, a multiplier, and an output terminal connected in cascade. The signals taken out in parallel from the output terminals are connected to the input of each multiplier via a plurality of cascade-connected delay devices, the outputs are inputted to the adder, and the signals taken out in parallel from the output terminals are The input signal is input to each multiplier through cascade-connected delay devices, and the output thereof is further input to the adder. The second method includes an input terminal, an adder, two multipliers, an adder, and an output terminal connected in cascade, and a signal extracted in parallel from the midpoint of the two multipliers is transmitted to a plurality of The signal is inputted to a plurality of multipliers via cascade-connected delay devices, and the outputs thereof are inputted to the respective adders.

[0009]

[Operation] Therefore, according to the present invention, when the configuration of the first method is adopted, the transfer function can be configured so that the denominator and numerator are symmetrical. , it has the effect of being able to reduce it by about half. In addition, when the configuration of the second method is adopted, the first method
As in the method described above, since the transfer function can be configured to have a symmetrical denominator and numerator, it has the effect that the amount of series can be reduced to about half when constructing a vertically symmetrical filter.

0010

[Embodiment] FIG. 1 shows a digital embodiment of the first embodiment of the present invention.
This shows the configuration of an equalizer circuit. In FIG. 1, 1 is an input terminal, 2, 4, 8, 9, 12, and 13 are multipliers, 3 is an adder, 5 is an output terminal, and 6, 7, 10, and 11 are delay devices, which are input terminals. 1 is input to a delay device 6 and a multiplier 2 in parallel. The delay device 6 provides a delay of one sampling period. Multiplier 2 performs multiplication with corollary b0. The output of multiplier 2 is connected to one input of adder 3. After passing through a multiplier 4, the output of the adder 3 is connected in parallel to an output terminal 5 and a delay device. Multiplier 4 performs multiplication with series a0. The output of delay device 7 is connected to multiplier 9 and delay device 11 in parallel. Multiplier 9 performs multiplication with series a1. The output of multiplier 9 is connected to one input of adder 3. delay device 11
The output of is connected to multiplier 13. Multiplier 13 performs multiplication with series a2. The output of multiplier 13 is connected to one input of adder 3. The output of the delay device 6 is connected to a multiplier 8 and a delay device 10 in parallel. The multiplier 8 performs multiplication with the corollary b1. The output of multiplier 8 is connected to one input of adder 3. The output of delay device 10 is connected to multiplier 12 . The multiplier 12 performs multiplication with the corollary b2. The output of multiplier 12 is connected to one input of adder 3.

Next, the operation of the first embodiment will be explained. According to the configuration of FIG. 1, a transfer function shown in equation 4 can be obtained.

0012

[Math 4]

On the other hand, the general formula of the analog second-order filter transfer function allows the construction of various analog filters, and by replacing this with a bilinear conversion formula, shelving high, shelving filters that can be constructed in analog - Various filter configurations such as low and peaking filters can be configured using digital signal processing. Note that the general expression and bilinear conversion expression of the transfer function of the analog second-order filter are shown by the equations 2 and 3, as explained in the conventional example. As described above, according to the first embodiment, the following equation 5, equation 6
By performing the substitutions shown in the formula and formula 7, the transfer function can be constructed so that the denominator and numerator are symmetrical. Therefore, when constructing a vertically symmetrical filter, it is necessary to hold one system. For example, the system of a symmetric filter can be given to the circuit shown in Figure 1 as a system by exchanging a and b and performing relatively simple calculations such as Equation 5, Equation 6, and Equation 7. For example, the amount of corollaries can be reduced by about half.

[0014]

[Math 5]

[0015]

[Math 6]

[0016]

[Math 7]

FIG. 2 shows the configuration of a digital equalizer circuit in a second embodiment of the present invention. Figure 2
, 21 is an input terminal, 22, 24, 28, 29,
32 and 33 are multipliers, 23 and 30 are adders, 25 is an output terminal, 26 and 27 are delay devices, and input terminal 1 is connected to one input of the adder 23. After passing through a multiplier 24, the output of the adder 23 is connected in parallel to a delay device 26 and a multiplier 22. The delay device 26 provides a delay of one sampling period. In the multiplier 24, the series a0
The multiplier 22 performs multiplication with the series b0. The output of multiplier 22 is connected to one input of adder 30. The output of adder 30 is connected to output terminal 25. The output of the delay device 26 is connected to a multiplier 29, a multiplier 28, and a delay device 27 in parallel. Multiplier 2
9 performs multiplication with the series a1, and multiplier 28 multiplies with the series b1. The output of the delay device 27 is sent to the multiplier 3.
3 and multiplier 32 in parallel. The multiplier 33 performs multiplication with the series a2, and the multiplier 32 multiplies the series b2.
Multiplication is performed. The outputs of multiplier 29 and multiplier 33 are each connected to the input of adder 23. Multiplier 2
The outputs of 8 and multiplier 32 are each connected to the input of adder 30.

Next, the operation of the second embodiment will be explained. According to the configuration of FIG. 2, the same transfer function (Equation 4) as in the first embodiment can be obtained. On the other hand, the general formula for the transfer function of an analog second-order filter allows various types of analog filters to be constructed, and by replacing this with a bilinear conversion formula, shelving high, shelving low, The configuration of various filters such as peaking filters can be configured by digital signal processing. These are the same as the first embodiment and the conventional example. In this way, according to the second embodiment, the equations 5, 6, 7
By performing the substitution shown in the equation, the transfer function can be constructed so that the denominator and numerator are symmetrical. Therefore, when constructing a vertically symmetrical filter, if one system has one system, it is possible to construct a symmetrical filter. After exchanging a and b, the series of can be obtained by performing relatively simple calculations such as Equation 5, Equation 6, and Equation 7, and feeding it as a series to the circuit shown in Figure 2. can be reduced by about half. Note that the circuits of the first and second embodiments may be connected in multiple stages as a peaking filter type. In this case, the effect of system number reduction can be increased,
Another advantage is that a frequency equalizer that can adjust the frequency characteristics of audio can be configured.

[0019]

Effects of the Invention As is clear from the first and second embodiments, the present invention allows the transfer function to be configured to have a symmetrical denominator and numerator, so when configuring a vertically symmetrical filter, one If the corollary numbers are held, the amount of corollary numbers can be reduced to about half by performing relatively simple calculations and applying them to the equalizer circuit as the corollary numbers.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a digital equalizer circuit in a first embodiment of the present invention.

FIG. 2 is a schematic block diagram of a digital equalizer circuit in a second embodiment of the invention.

FIG. 3 is a schematic block diagram of a conventional digital equalizer circuit.

FIG. 4 is a diagram showing waveforms of a vertically symmetrical filter.

[Explanation of symbols]

1, 21, 41...input terminal, 2, 4, 8, 9, 12
,13,22,24,28,29,32,33,42,
48, 49, 52, 53... Multiplier, 3, 23, 30
, 43... Adder, 5, 25, 45... Output terminal,
6, 7, 10, 11, 26, 27, 46, 47, 50,
51...Delay device.

Claims (2)

[Claims] 1. A device comprising: an input terminal, a multiplier, an adder, a multiplier, and an output terminal connected in cascade; signals taken out in parallel from the input terminal are each multiplied via a plurality of cascade-connected delay devices. connect to the input of the adder, input its output to the adder, and take out the signals in parallel from the output terminal,
1. A digital parametric equalizer circuit, comprising a plurality of cascaded delay devices each connected to an input of a multiplier, the output of which is input to the adder. [Claim 2] An input terminal and an adder connected in cascade;
It has two multipliers, an adder, and an output terminal, and the signal taken out in parallel from the midpoint of the two multipliers is input to the plurality of multipliers via a plurality of cascade-connected delay devices, and the output thereof is A digital parametric equalizer circuit, characterized in that each input is input to the adder.