JPH04335576A - Semiconductor device - Google Patents

Abstract

PURPOSE:To produce a semiconductor device which can obtain a gate insulating film having different film thicknesses on the same substrate simply and without damaging the reliability of the gate insulating film. CONSTITUTION:The constitution of the title semiconductor device is provided with the following: a gate insulating film 4 on a semiconductor substrate 1 or 2; and at least two of a first gate electrode and a second gate electrode 10A, 10B on the gate insulating film 4. The first and second gate electrodes 10A, 10B are featured in the following manner: they are of the same conductivity type as that of a channel 14; they are provided with at least two kinds of impurity concentrations; and at least the gate electrode whose concentration is thinnest is provided with a region 5 or 5' in which a depletion region is expanded under an actual operating voltage. By this constitution, the gate electrode 10A or 10B can be depleted and the film thickness of the gate insulating film can electrically be changed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to semiconductor devices.
In particular, MOSFETs that can electrically change the thickness of the gate insulating film.
Regarding ET.

0002

2. Description of the Related Art Integrating MOSFETs with gate insulating films of different thicknesses in one semiconductor integrated circuit device means that there are multiple potentials applied to the gate electrodes, May be required to improve Jin. The following methods are available for forming gate insulating films of different thicknesses on the same substrate.

For example, after obtaining a gate oxide film by oxidizing the surface of the substrate, only the areas where the gate oxide film is desired to be thick are covered with resist, and the portions of the gate oxide film that are not covered with resist are removed. a portion where the gate oxide film was removed by removing the resist, then oxidizing the substrate again, and removing the gate oxide film;
There is a so-called "double oxidation method" in which a gate oxide film having a different thickness is obtained in the unremoved portion. As another method, a first gate oxide film is formed on the substrate, a first gate electrode is further formed on the first gate oxide film, and then a thick gate oxide film is formed. From the top of the board where you want to form
The conductive layer, etc. that constituted the first gate electrode is removed, and the first gate electrode is removed.
A second gate oxide film thicker than the first gate oxide film is formed on the substrate, and a second gate electrode is further formed on the second gate oxide film. "Gate gate electrode processing method"
There is.

0004

However, the above-mentioned double oxidation method and double gate electrode processing method have the following problems.

First, in the double oxidation method, since the resist is placed directly on the gate oxide film, the gate oxide film takes in harmful impurities such as heavy metals contained in the resist. According to this, the reliability of the oxide film deteriorates.

[0006] Furthermore, in the double gate electrode processing method,
The gate oxide film must be formed twice and the gate electrode must be formed twice. According to this, the manufacturing process of the semiconductor integrated circuit device becomes complicated.

The present invention has been made in view of the above-mentioned points, and its object is to easily and without impairing the reliability of the gate insulating film, film having different thicknesses can be formed on the same substrate. The object of the present invention is to provide a semiconductor device from which a gate insulating film can be obtained.

[0008]

[Means for Solving the Problems] A semiconductor device of the present invention includes a semiconductor substrate, a gate insulating film formed on the substrate, and a polysilicon film formed on the gate insulating film. The gate electrode is used as a gate electrode, and the gate electrode is placed in this polysilicon.
a first gate having the same conductivity type as carriers induced in the substrate under the insulating film, having at least two types of impurity concentrations, and having a region in which a depletion layer expands under an actual operating voltage;
A second gate electrode having a higher impurity concentration in polysilicon than a first gate electrode in which a depletion layer does not expand, and a second gate electrode in which a depletion layer does not expand. Features.

Furthermore, among the gate electrodes, even the one with the lowest concentration is in a degenerate state, and the first and second gate electrodes are
The feature is that the work function of each of the two electrodes is constant.

[0010] Further, semiconductor devices of other embodiments include
The gate electrode is connected to the word line, and is composed of a gate electrode of the same conductivity type as the carriers of the channel and having a first impurity concentration and having a region in which a depletion layer expands under an actual operating voltage. 2
a transfer gate transistor, a first bit line connected to one of the source/drain of the first transfer gate transistor, and a first bit line connected to one of the source/drain of the second transfer gate transistor. a second bit line connected to one end, one end connected to the first power supply, and the other end connected to the other source/drain of the first transfer gate transistor; a first load connected to the second transfer gate transistor; one end connected to the first power source;
a second load connected to the other side of the source/drain;
A gate is connected to the other of the source/drain of the second transfer gate transistor, and one of the source/drain is connected to the source/drain of the second transfer gate transistor.
A first gate electrode connected to the other end of the drain and the other end of the second load, the gate electrode having the same conductivity type as the carriers of the channel and having a second impurity concentration higher than the first impurity concentration. A gate is connected to the other of the source/drain of the driver transistor and the second transfer gate transistor, and one of the source/drain is connected to the source/drain of the first transfer gate transistor. - a second driver transistor connected to the other end of the source/drain and the other end of the first load and configured with a gate electrode having the same conductivity type as carriers of the channel and having the second impurity concentration; It is characterized by comprising the following.

[0011]

[Operation] According to the above semiconductor device, the impurity concentrations of the first and second gate electrodes are different, and at least the one with the lowest concentration has a region where the depletion layer expands under the actual operating voltage. There is. Thereby, by depleting the gate electrode, the thickness of the gate oxide film can be changed not physically but electrically. Therefore, games with different film thicknesses
Instead of forming each gate insulating film, by simply forming one gate insulating film and changing the impurity concentration of the gate electrode,
Transistors with gate insulating films of multiple thicknesses,
can be obtained on the same substrate.

[0012] Furthermore, if even the thinnest impurity concentration is made to be in a degenerate state and the work functions of the first and second gate electrodes are made the same, the threshold value of the transistor will not change even if the impurity concentration changes. This makes the process more stable for mass production.

Furthermore, according to another aspect of the semiconductor device, the gate electrodes of the first and second driver transistors are of the same conductivity type as the channel carriers, have the first impurity concentration, and are under the actual operating voltage. The gate electrodes of the first and second driver transistors are of the same conductivity type as the channel and have a second impurity concentration higher than the first impurity concentration. It is made up of things. That is, since the film thickness of the gate insulating film can be electrically changed, the driving capabilities of the transfer gate transistor and the driver transistor can be changed respectively. Therefore, it is possible to increase the β ratio between the transfer gate transistor and the driver transistor, and the stability of the memory cell can be improved.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described by way of embodiments with reference to the drawings. 1 to 7 are cross-sectional views showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

First, a p-type well 2 is formed in an n-type silicon substrate 1 having a specific resistance of about 1 to 2 Ω·cm. Then,
An oxide film 3 for element isolation is formed on the substrate 1 by selective oxidation. Next, the substrate 1 is treated in a dry oxygen atmosphere at a temperature of about 800 DEG C. to form a gate oxide film 4 with a thickness of about 110 angstroms on the substrate 1 (FIG. 1). Next, a polysilicon layer 5 having a thickness of approximately 1000 angstroms is formed over the entire upper surface of the substrate 1 by the LPCVD method (FIG. 2).

Next, arsenic ions 6, which are n-type impurities, are heated at an acceleration voltage of 30 keV and a dose of 1.0×10 15 cm.
Ions are implanted into the polysilicon layer 5 under the conditions of -2 (
Figure 3).

Next, the region where gate depletion is to occur is covered with a resist 7. Next, using the resist 7 as a mask, arsenic ions 8, which are n-type impurities, are heated at an accelerating voltage of 30k.
Ions are selectively implanted into the polysilicon layer 5 under the conditions of eV and a dose of 5.0×10 15 cm −2 . As a result, the polysilicon layer 5 has a region 5 with a high impurity concentration.
' can be selectively obtained (Fig. 4). Next, a tungsten silicide layer 9 having a thickness of approximately 2000 angstroms is formed on the entire upper surface of the substrate 1 by sputtering (FIG. 5).
).

Next, through a lithography process, the silicide layer 9 and the polysilicon layer 5 are selectively etched by anisotropic etching to form the gate electrodes 10A, 10.
get B. Next, a p-channel MOSFET (not shown)
The formation region is covered with a resist (not shown). Next, arsenic ions, which are n-type impurities, are selectively implanted into the p-type well 2 under conditions of an acceleration voltage of 50 keV and a dose of 2.0×10 15 cm −2 . This allows n-channel MOS
FET source/drain regions 11 are obtained (FIG. 6)
. Next, although not particularly shown, an n-channel MOSF
The ET formation region is covered with a resist, and boron ions, which are p-type impurities, are applied at an acceleration voltage of 15 keV and a dose of 2.0×1.
A source/drain region of a p-channel MOSFET is obtained by selectively implanting into the n-type substrate 1 under the condition of 0.015 cm -2 . Next, in order to activate the implanted arsenic ions and boron ions, the temperature was set at 900°C in a nitrogen atmosphere.
The substrate 1 is annealed at a temperature of 60 minutes.

Next, the interlayer insulating film 11 is formed by the CVD method.
is formed on the entire upper surface of the substrate 1. Next, a contact hole 12 communicating with the source/drain region 11 is formed in the interlayer insulating film 11. Next, an aluminum layer is formed on the interlayer insulating film 11 by sputtering, and then the aluminum layer is patterned to obtain a wiring layer 13 (
Figure 7).

In the semiconductor device having the above structure, the polysilicon layer 5 constituting the gate electrode 10A and the gate electrode 1
The impurity concentration is different from that of the polysilicon layer 5' constituting 0B. In this way, by changing the amount of impurity doped into the polysilicon layer 5, the amount of the depletion layer formed in the polysilicon layer 5 can be changed, so the effective thickness of the gate oxide film can be changed. be changed. Therefore, by simply changing the amount of impurity doped into the polysilicon layer 5, the thickness of the gate oxide film can be increased without complicating the process or reducing the reliability of the gate oxide film. Different transistors Tr1 and Tr2 can be obtained on the same substrate. For example, in a portion of polysilicon layer 5 where the impurity concentration is low (gate electrode 10A), a depletion layer is formed in polysilicon layer 5, so that the thickness of the gate oxide film can be effectively increased. For example, under the conditions of the above embodiment, the effective thickness of the gate oxide film is about 135 angstroms.

In the above embodiment, the n-channel MOS
Although the example in which the effective gate oxide film is changed has been described only for FETs, it goes without saying that the present invention can also be applied to p-channel type MOSFETs. p channel type M
When this invention is applied to an OSFET, the following will occur.

That is, in FIG. 3, boron ions, which are p-type impurities, are implanted into the polysilicon layer 5 instead of arsenic under conditions of an acceleration voltage of 5 keV and a dose of 1.0×10 15 cm −2 . Next, in FIG. 4, a polysilicon layer is formed using boron ions instead of arsenic at 5 keV and a dose of 5.0 x 1015 cm-2 only in the region where a thin gate oxide film is desired to be formed. 5, type selectively. In this way, even if the p-channel MOSFET is
The oxide film can have two or more different thicknesses. It goes without saying that in the case of a p-channel MOSFET, the polysilicon layer 5 is formed not above the p-type well 2 but above the n-type substrate 1. Also, C
When this invention is applied to a MOS type device, if an n-type impurity is implanted into the polysilicon layer 5 in the region of the n-channel MOSFET and a p-type impurity is implanted in the region of the p-channel MOSFET. The gate oxide films of both channel and p-channel MOSFETs can have two or more different thicknesses. Further, as in the present invention, in order to change the doping amount to the polysilicon layer 5 and generate a depletion layer in the polysilicon layer, an n-channel MOS
In the case of a FET, the polysilicon layer 5 is doped with an n-type impurity of the same conductivity type as the carriers of the channel 14, and
Similarly, in the case of channel type MOSFET, channel 1
It is necessary to dope the polysilicon layer 5 with a p-type impurity having the same conductivity type as the carrier No. 4.

Furthermore, if the amount of doping into the polysilicon layer 5 is too thin, the polysilicon layer 5 will be in a non-degenerate state;
Due to the fluctuation of impurities in the polysilicon layer 5, the work function of the gate electrode changes, and the threshold value of the MOSFET may change. If the threshold value of the MOSFET changes, it may cause problems in terms of circuit margin. Such fluctuations in the threshold value occur when the impurity concentration in the polysilicon layer 5 becomes approximately less than 10<19 >cm<-3>. However, the impurity concentration of the polysilicon layer 5 is 1019 cm-
If it is about 3, a depletion layer can be formed in the polysilicon layer 5 when the transistor is turned on. From this point, the impurity concentration of the polysilicon layer 5 is set to 101
By setting the polysilicon layer 5 to a degenerate state by setting it to 9 cm -3 or more, fluctuations in the threshold value of the MOSFET can be prevented. Note that if the thickness of the polysilicon layer 5 and the ion implantation conditions are as in the above embodiment, the portion with a low impurity concentration (gate
Even in the case of the second electrode 10A), a concentration on the order of 10<19 >cm<-3> can be ensured even if the amount of impurity diffused into the silicide layer 9 is considered. Next, an example in which the semiconductor device according to the present invention is applied to a static RAM memory cell will be described. Figure 8(a) shows a static type RA with high resistance load.
FIG. 3B is an equivalent circuit diagram of an M memory cell; (b) is an equivalent circuit diagram of a CMOS static RAM memory cell.

For example, high resistance load static type RA
In the M memory cell, in order to improve the stability of the cell,
The ratio of β of driver transistors Tr10 and Tr11 to β of transfer gate transistors Tr12 and Tr13 is increased. Conventionally, the channel width of the driver transistors Tr10 and Tr11 is made wider than that of the transfer gate transistors Tr12 and Tr13, or
Or transfer gate transistors Tr12, T
The channel length of r13 is determined by the driver transistor Tr10.
, making it longer than Tr11, or making it longer than Tr11. However, both of these methods change the area of the transistor, increasing the cell size. Furthermore, as a method of increasing the β ratio without increasing the cell size, transfer gate transistors Tr12,
There is a method of making the gate oxide film of Tr13 thicker than that of driver transistors Tr10 and Tr11, but as mentioned earlier, this method complicates the process or reduces the reliability of the gate oxide film. There is a problem with it falling off.

In this regard, if the present invention is applied to a static type RAM, the transfer gate can be used without increasing the cell size or reducing the reliability of the gate oxide film.
The β ratio between the driver transistor and the driver transistor can be increased. For example, in the semiconductor device formed as in the above embodiment, the actual gate oxide film of both transistors Tr1 and Tr2 is 110 angstroms. However, if the thickness of the polysilicon layer 5 and the amount of ion implantation are as in the above embodiment, the transistor Tr shown in FIG.
The effective thickness of the gate oxide film of No. 1 is approximately 135 angstroms. Further, in the transistor Tr2, the thickness of the gate oxide film remains approximately 110 angstroms. Therefore, the transistor Tr1 is replaced with transfer gate transistors Tr12 and Tr13 shown in FIG. 8(a).
The transistor Tr1 is used as the driver transistor T
If it is used for r10 and Tr11, the following results will be obtained. For example, if the β ratio on the cell layout is 3, 3 × (135/110) = 3.68

[
In this way, the present invention can be applied to static type RA.
If applied to an M memory cell, the change in gate oxide film thickness (135/110) can be added to the β ratio that originally exists due to the cell layout, so β
The ratio can be greatly improved, and the stability of the memory cell can be further improved. In addition, in FIG. 8, BL, BL-(-
(indicates an inverted signal) respectively indicate a bit line, WL indicates a word line, and L indicates a load.

Application to static type RAM memory cells is possible not only to high resistance load type but also to CMOS type static type RAM memory cells as shown in FIG. 8(b). In this case as well, the transistor Tr1 with a thicker effective gate oxide film thickness as shown in FIG. It is sufficient to use the transistor Tr2.

[0028]

As explained above, according to the present invention, gate insulating films of different thicknesses can be easily formed on the same substrate without impairing the reliability of the gate insulating film. It is possible to provide a semiconductor device that can be used.

[Brief explanation of the drawing]

FIG. 1 is a first cross-sectional view showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is a second cross-sectional view showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 3 is a third cross-sectional view showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 4 is a fourth cross-sectional view showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 5 is a fifth cross-sectional view showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 6 is a sixth cross-sectional view showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 7 is a seventh cross-sectional view showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 8 is a diagram showing a semiconductor device to which the present invention can be applied (
(a) is an equivalent circuit diagram of a static RAM memory cell with a high resistance load, (b) is a CMOS static RA
An equivalent circuit diagram of an M memory cell.

[Explanation of symbols]

1... N-type silicon substrate, 2... P-type well region, 4... Gate
oxide film, 5, 5'... polysilicon layer, 9... silicide layer, 10A, 10B... gate electrode, 14... channel, T
r10, Tr11...driver transistor, Tr12,
Tr13...Transfer gate transistor. BL,B
L-...bit line, WL...word line, L...load.

Claims (3)

[Claims] 1. A semiconductor substrate, a gate insulating film formed on the substrate, and polysilicon formed on the gate insulating film are used as gate electrodes, and in this polysilicon, a first gate having the same conductivity type as carriers induced in the substrate under the gate insulating film, having at least two types of impurity concentrations, and having a region in which a depletion layer expands under an actual operating voltage; 1. A semiconductor device comprising: an electrode; and a second gate electrode having a higher impurity concentration in polysilicon than the first gate electrode in which a depletion layer does not expand. 2. The semiconductor device according to claim 1, wherein the first and second gate electrodes are in a degenerate state even if they have the lowest concentration, and each has a constant work function. 3. The gate electrode is connected to a word line and has a first impurity concentration, which has the same conductivity type as carriers of the channel and has a region in which a depletion layer expands under an actual operating voltage. a first bit line connected to one of the source/drain of the first transfer gate transistor;
the source of the second transfer gate transistor;
a second bit line connected to one end of the drain;
a first load having one end connected to a first power supply and the other end connected to the other source/drain of the first transfer gate transistor; have,
a second load having one end connected to the first power supply and the other end connected to the other source/drain of the second transfer gate transistor; - A gate is connected to the other end of the source/drain, and one of the source/drains is connected to the other end of the source/drain of the second transfer gate transistor and the other end of the second load. a first driver transistor connected to a gate electrode having the same conductivity type as the channel carrier and having a second impurity concentration higher than the first impurity concentration; and the second transfer gate. A gate is connected to the other source/drain of the transistor, and one of the source/drain is connected to the other source/drain of the first transfer gate transistor and the first load. A semiconductor device comprising: a second driver transistor connected to the other end and configured with a gate electrode having the same conductivity type as the channel carrier and having the second impurity concentration.