JPH0433574A - inverter device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an inverter device in which a plurality of unit inverters are connected in parallel and operated by performing current balance control.

[Conventional technology]

FIG. 4 shows, for example, Anyo Denki Nα2, 1987, p.

105-112 is a specific circuit diagram showing the configuration for one phase of the conventional current balance control shown in "Model expansion of high-performance inverter drive series for systems", and in the figure, 150 and 250 are base drive circuits, 300,3
01, 305, 306 are subtracters, 302, 307 are current controllers, 303, 308 are comparators, 304
is a triangular wave generator that generates a carrier wave (modulated wave), 31
0 is a current reference command input from the outside.

FIG. 5 is a configuration diagram of a conventional voltage type inverter in which two unit inverters are connected in parallel.
1 is a DC voltage source, and 10 is a first unit inverter comprising transistors 101 to 106 and diodes 107 to 112. Also.

20 is a second unit inverter and transistors 201 to 2
06 and diodes 207-212. ]2
1 to 123 and 221 to 223 are respectively installed on the output side of the unit inverter (current transformers C'F), and 1-31 to 133 are phase reactors 1 to 1.

Next, the operation will be explained. First, the first and second unit inverters 10 and 20 are connected to a common voltage source 1, respectively. The outputs of the unit inverters are connected in parallel via interphase reactors 131-133. A current transformer 121 for current detection is used to balance the output currents of the first unit inverter 1° and the second unit inverter 20.
~ ] 23 and 221 to 223 are provided.

Details of the current balance control for this one phase will be explained with reference to FIG. 4. First, the current reference command right 310 input from the outside and the current transformer 121 from the output side of the unit inverter.
The subtracter 300 takes the difference from the output current detected by the subtracter 300 and inputs the deviation to the current controller 302. The current controller 302 changes the output so that the output current of the unit inverter 1.0.20 follows the current reference command 310.

By inputting the deviation between the output of the current controller 302 and the output of the carrier signal generator 304 to the subsequent comparator 303 via the subtracter 301, a PWM command is obtained for the base drive circuit 150. The base drive circuit 150 is connected to the PW output from the comparator 303.
Transistors 101 and 102 are driven according to the M command.

The second unit inverter 20 is also controlled in the same manner as the first unit inverter]-0. By controlling in this way, the output currents of the first unit inverter 10 and the second unit inverter 20 follow the current reference command 310, and as a result, the output currents of the two inverters are balanced.

[Problem to be solved by the invention]

Since conventional inverter devices are configured as described above, it is necessary to provide a current controller for each unit inverter, which increases the number of parts and complicates the circuit configuration, and also requires a relatively large inductance output. Due to the need for parallel inverters, an interphase reactor method was used (there were constraints such as the fact that the number of A1 inverters connected in parallel had to be an even number).

This invention was made in order to solve the problems described in "-", and provides an inverter device that has a simple circuit configuration, has a small number of parts, can perform current balance control, and can connect any number of unit inverters in parallel. The purpose is to obtain.

[Means to solve the problem]

The inverter device according to the present invention includes a PWM signal generation circuit that applies a PWM control signal to one transistor of each unit inverter, and a PWM signal generator that balances the output current of the unit inverter to the other transistor of the unit inverter.
a current balance control circuit that provides a control signal; a subtracter that subtracts each current value of a current transformer that detects the output current of each of the unit inverters; and if one of the unit inverters is a reference inverter, the other Compare the current value of the unit inverter and the reference unit inverter, and if the current value is larger than that of the reference unit inverter, make the PWM pulse width applied to the positive side transistor shorter than the pulse width applied to the negative side transistor, If the PWM pulse width is smaller than the reference unit inverter, the PWM pulse width applied to the positive side transistor is made longer than the pulse width applied to the negative side transistor.

[Effect]

The inverter device according to the present invention includes one PWM signal generation circuit for a plurality of unit inverters, inputs the output signal of the PWM signal generation circuit to a pulse width controller, and controls the output current of each unit inverter. Detected by a current transformer, the current value (output current) of each unit inverter is compared with the current value of the unit inverter as a reference, and if it is larger than this, the PWM pulse width applied to the positive side transistor is changed to the negative side transistor. The pulse width of the current balance control circuit is made shorter than the pulse width applied to the positive side transistor, and if it is smaller than this, the PWM pulse width applied to the positive side transistor is made longer than the pulse width applied to the negative side transistor. Since current balance control is performed by the controller, current balance can be achieved with a simple circuit, and any number of unit inverters can be connected in parallel.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows one phase when two unit inverters are connected in parallel. In the figure, 2 is the first unit inverter, 3 is the second unit inverter, 21. ．． 22,3
1.32 is the base drive circuit, 23, 24, 33.3
4 is a transistor, 4 and 5 are current transformers, 6 and 7 are ACs 1 to 1 provided on the output side, and 9 is a T that outputs a PWM voltage waveform.
) WM signal generation circuit; 8 is a current balance control circuit according to the present invention;

FIG. 2 is a detailed diagram of the current balance control circuit 8.

In the figure, 84.85 is a subtractor, 87°88 is a pal;
(It is a width controller.

FIG. 3 is an operational waveform diagram of the pulse width controllers 87 and 88.

Next, the operation will be explained. Masu PWM signal generation circuit 9
The output is input to the current balance control circuit 8 via the signal line 181. Further, the signal lines 182 and 183 are connected to the current transformer 4
The output current of the 111th inverter detected by and 5 is input to the current balance control circuit 8. Here, the first
Let unit inverter 2 be the reference inverter.

First, apply PW to the first unit inverter 2, which is the reference.
The output 181 of the M signal generation circuit 9 is directly input manually.

The output current value of the first unit inverter 2 and the second
The unit of output current value of inverter 3 and the current transformer 4, 5
and the output signals 1.82, 183 are sent to the subtracter 84.
Enter. At this time, since the calculation result of the subtracter 84 is positive, which means that the output current is smaller than that of the first li-order inverter 2, which serves as a reference, the pulse width given to the base drive circuit 21 is controlled to be longer. . Further, if the output of the subtracter 84 is negative, the current value of the second unit inverter 3 is determined from the current value of the first unit inverter 2 which is the reference.
Since the output current is large, the pulse width applied to the base drive circuit 31 is controlled to be short. This control is performed by a pulse width controller 87. Signal 1-
85 and the output 186 of the pulse width controller 87 are input to the base drive circuits 21.31 of the first and second +4i inverters 2 and 3, respectively, and drive the positive side 1-hylang resistors 2:3.33. If the pulse width of the 1-transistor 23, 33 on the positive side is made longer, the current flowing out of the inverter device increases, and if the pulse is made shorter, it decreases, so that current balance control becomes possible. When the output current becomes unbalanced, circulating current flows between the unit inverters and losses also increase.

Generally, the pulse width imbalance that causes current imbalance is about 1 to 2'ALsec. Therefore, the time required to lengthen or shorten the pulse width may be several seconds.

On the other hand, the margin time for preventing short circuit between phases is 30 to 50 seconds.
Since there is QC, even if the pulse width control according to the present invention is performed, there is no effect on the whole.

In addition, in the case of this invention, since the pulse width is only lengthened or shortened for a very short time, the balance accelerators 6 and 7 need only have small inductance, and the voltage drop can be ignored even if the inductance is provided individually for each unit inverter. That's about it.

FIG. 3 is a waveform diagram showing an example of the operation of the pulse width controller 87, where a is the leading edge (IIJ wide pulse W) with respect to the reference pulse SP.
This is an example in which control is applied to I)) and the trailing edge (11J narrow pulse NP). In addition, in b, control is similarly applied only to the leading edge, and in C, the pulse width is controlled only to the trailing edge. a shows the best properties, but in some cases,
Considerable effects can be obtained even with c. Furthermore, the broken line in Figure 2 is! This shows the configuration of the balance control circuit 8 when three 4'L inverters (odd number) are connected in parallel.As shown in the figure, by simply adding a subtracter 85 and a pulse width controller 88, the unit inverter can be The number of parallel circuits can be increased.

In the above embodiments, a transistor inverter has been described, but a self-excited inverter may also be used, and the elements and circuit configuration used are not limited.

Further, in the above embodiment, only the P side arm is controlled, but it may be configured to control only the N side arm or both the P side and the N side, and the same effects as in the above embodiment can be obtained.

Moreover, although the balance glue handle is provided for each unit inverter, it is of course possible to configure it with an interphase reactor if the number of unit inverters in parallel is an even number.

〔Effect of the invention〕

As described above, according to the present invention, one PWM signal generation circuit is provided for a plurality of unit inverters, and
The output current of each unit inverter is detected by a current transformer, and if the output current of each unit inverter is thicker than the output current of the standard unit inverter, the positive side PWM pulse is shortened.
In addition, if it is small, the current balance control is performed using the pulse width controller of the current balance control circuit so that the positive side PWM pulse is lengthened, which greatly simplifies the control circuit.
Furthermore, since each inverter is provided with an individual balancing grid, any number of unit inverters can be connected in parallel, resulting in the device being compact and inexpensive.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of current balance control of an inverter device according to an embodiment of the present invention, FIG. 2 is a configuration diagram of the current balance control circuit of FIG. 1, and FIG. 3 is a diagram of the pulse width controller of FIG. 2. FIG. 4 is a block diagram of a conventional current balance control circuit, and FIG. 5 is a block diagram of a conventional current balance control circuit in which two m-order inverters are connected in parallel. In the figure, 1 is a voltage source, 2 and 3 are unit inverters, and 4 is a voltage source.
, 5 is a current transformer, 6 and 7 are reactors, 8 is a current balance control circuit, 9 is a PWM signal generation circuit, 84 is a subtracter, 8
7.88 is a pulse width controller=11-. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Patent applicant Mitsubishi Electric Corporation

Claims (1)

[Claims] In an inverter device that operates by connecting a plurality of unit inverters in parallel to a voltage source and connecting the outputs of the unit inverters in parallel via a reactor, a PW that applies a PWM control signal to one transistor of each unit inverter.
M signal generation circuit; and a current balance control circuit that provides a PWM control signal for balancing the output current of the unit inverter to the other transistor of each of the unit inverters, the current balance control circuit controlling the output current of each of the unit inverters. A subtracter that subtracts each current value of the current transformer that detects the current transformer, and one of the unit inverters as a reference inverter, compares the current value of the other unit inverter with that of the reference unit inverter, and calculates the reference value. If the unit inverter is larger than the PWM applied to the positive transistor,
Make the pulse width shorter than the pulse width applied to the negative side transistor, and if it is smaller than the reference unit inverter, make the PWM pulse width applied to the positive side transistor longer than the pulse width applied to the negative side transistor. An inverter device comprising a pulse width controller.