JPH04337732A - Formation of pattern - Google Patents

Abstract

PURPOSE:To form the resist pattern to be used for producing compd. semiconductor devices, such as MESFETs in particular, for which fine sizes for gate of <=0.5mum are required with the pattern forming method using a resist. CONSTITUTION:The isolated resist pattern including the fine patterns is formed by using the steep light intensity distribution made at the edge of a phase shifter 13 of a mask including phase shifters 13 in the pattern. The unnecessary parts formed by the phase shifters 13 are removed by superposing another pattern 12 and exposing the resist. This method is effective for forming the fine patterns of <=0.3mum having the isolated patterns. The processing time is shortened drastically to <=1/6 the processing time of the conventional methods which form the patterns by an EB plotting device.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern forming method using a resist, and more particularly to a pattern forming method of a photoresist used in manufacturing compound semiconductor devices requiring fine dimensions of 0.5 μm or less.

0002

2. Description of the Related Art Photolithography is positioned as a major technology for advancing miniaturization of dimensions in semiconductor manufacturing processes. Currently, the minimum dimensions of 0.4 to 0.5 μm can be handled using regular i-line or excimer laser tapers, but when forming resist patterns with dimensions smaller than this, the throughput decreases. It was necessary to use an electron beam lithography system. In contrast, using a conventional taper,
A phase shift method has been proposed and studied to improve this utilization technique. For example, Nikkei Micro Devices, July 1990 issue, pages 108 to 114.
stated on the page. As can be seen, this phase shift method has been applied to reticles with regularly arranged or closely spaced patterns. but,
For example, GaAs MESFET (Metal Sch
ottky Field Effect Trans
Conventional phase shift methods have not been effective for masks consisting of a group of relatively isolated fine-sized patterns, such as gate patterns of ICs using the same method, and have not been used.

0003

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and form an isolated fine resist pattern by applying a phase shift method.

0004

Means for Solving the Problems To achieve the above object, the resist pattern forming technique according to the present invention uses the following means.

Isolated resist pattern including fine pattern
To form a pattern group, a pattern group including a phase shifter is used in the mask. For resist patterns smaller than approximately 0.4 microns, the resist pattern is formed using the steep light intensity distribution created at the edge of the phase shifter of the mask, and the unnecessary portion created at the edge of the phase shifter is removed from other resist patterns. This method uses a method of removing by overlapping irradiation using a mask pattern to form a desired pattern.

[0006]

[Operation] The light intensity distribution at the edge of the phase shifter 102 (in the case of a phase angle of 180°) on the glass substrate 101 was obtained by computer simulation, and the results are shown in FIG. It can be seen that the light intensity distribution is steep at the edges, and the light intensity at the center is zero. When a positive resist is exposed using this mask, a resist pattern having a size of 0.3 μm or less can be formed on the contour of the mask without reducing the thickness of the resist. For negative resist, resist groove (space)
can be formed. Since the light intensity distribution in FIG. 1 is steep, there is little shift in resist dimension with respect to the exposure amount. For this reason, 0.
A dimension of 3 μm or less can be easily achieved by controlling the exposure amount.

[0007]

[Examples] The present invention will be explained in detail below with reference to Examples.

[Embodiment 1] FIG. 2 shows a gate layer pattern of a MESFET used in GaAs IC and LSI. An example of two gate patterns is shown here, and each gate pattern consists of an FET section 1 with a gate length (Lg) of 0.3 μm and a pad section 2 for taking out an electrode. With a conventional mask pattern using Cr or the like for the light-shielding part, it was not possible to transfer such a narrow gate length pattern onto the resist due to the resolution limit of i-line photolithography, but the pattern formation according to the present invention The law made this possible. This method will be described below.

FIGS. 3 and 4 show examples carried out to obtain the gate layer pattern shown in FIG. These show two mask patterns, and a gate pattern can be formed on the wafer by a composite image obtained from the two masks. FIG. 3 shows a mask #A comprising a light shielding pad pattern 12 made of Cr, chromium oxide, etc., and a phase shift pattern (phase shifter) 13 made of a silicon oxide film on a glass substrate 11. As can be seen from the figure, the phase shift pattern 13 and the Cr pad pattern 1
No. 2 has a partially overlapping region, and these are formed in separate steps. Further, FIG. 4 shows a mask #B in which a hole pattern 23 is formed in a light shielding layer 22 made of Cr, chromium oxide, etc. on a glass substrate 21. A layer of Cr or chromium oxide completely blocks the transmission of light, and a phase shifter layer made of silicon oxide film completely transmits light, but it has the role of delaying the phase of the light, and in this example, the phase shifter layer consists of a silicon oxide film that completely transmits light. The thickness of the phase shifter layer is determined so that the angle is 180°. Alignment marks 10, 20 are arranged on each mask. An example of transferring a pattern onto a resist on a wafer using these two masks is shown in FIGS. 5 and 6. FIG. 5 shows positive resist patterns 31 and 32 exposed using mask #A shown in FIG. As described in FIG. 1, the principle of using a phase shifter is that when a wafer is exposed using a mask including the phase shift pattern 13 shown in FIG.
．． It is formed with a width of 3 μm. With mask #A, resist patterns in unnecessary regions 33 and 34 are formed at the same time, but in order to remove these and divide them into two gate patterns, exposure is performed using mask #B shown in FIG. 4. After these two exposures, a development process is performed to form gate patterns 36, 3 having desired dimensions as shown in FIG.
7 on the wafer.

[Embodiment 2] Next, another embodiment according to the present invention will be described with reference to FIGS. 7 and 8.

This is an example suitable for a case where pattern formation with higher positional accuracy than the example described in the first embodiment is required. The mask in FIG. 7 includes phase shifters 41, 42, 43 and C.
It is composed of r masks 44, 45, and 46. As can be seen from the figure, the gate portion of the FET formed by the phase shifter uses sides of each shifter in the same direction, so that the machining accuracy of the phase shifter is unlikely to affect the alignment accuracy of the FET. FIG. 8 shows a mask pattern for erasing unnecessary resist patterns, similar to FIG. 6, with windows 51, 52,
53 is open.

[Embodiment 3] Next, an embodiment for forming dual gate patterns 61 and 62 using the present invention will be described. In a conventional dual gate FET having a control gate adjacent to one gate, the closer the distance between the two gates, the higher the sensitivity becomes. Therefore, as shown in FIG. 9, a phase shifter 63 and Cr masks 64 and 65 according to the present invention are arranged in mask #A. The minimum dimension Lp of the phase shifter in this configuration is 0.5 μm on the wafer. The resist pattern dimensions obtained by this are as shown in Figure 10, with a gate length of 0.3 μm.
, close dual gate putter with 0.3μm spacing
The holes 81 and 82 are easily formed. Unnecessary portions of the resist may be exposed using a separate mask as in the first embodiment. A WSi gate metal 83 on a GaAs substrate 84 is processed using the resist patterns 81 and 82 as a mask to form a dual gate.

[Embodiment 4] Next, an embodiment in which a desired fine pattern is formed by using a single mask and exposing it twice with shifts will be described with reference to FIGS. 11 and 12. This is a phase shifter 91 and a Cr pattern 9 in one mask.
2, a Cr pattern 93 for erasing unnecessary resist patterns, and a blank pattern 94 for erasing this Cr pattern 93, and each pattern is arranged at a distance S as shown in FIG. There is. An explanatory diagram of how to obtain a desired pattern using this mask is shown in FIG. This is a diagram of a resist pattern. First, when the mask shown in FIG. 11 is transferred, resist patterns 95, 96, and 97 shown by solid lines are formed. Next, when the same mask is exposed by shifting it by a distance S (to the left in the figure), the patterns 98, 99, and 100 shift to the positions shown by the broken lines, so the resist in the twice-exposed area disappears, and in this example, One desired gate pattern 5 is obtained. In this embodiment, the direction in which the mask is shifted is described as an example of left and right, but the direction is not limited to this. Also, Figure 1
As can be seen from 1, in order to obtain one pattern, the width W
For example, the width of the phase shifter on the wafer is about 2 μm, the spacing between both patterns S is about 5 μm, and the width W is required.
has a value of approximately 15 μm. This can be sufficiently used, for example, in the case of a single FET or an isolated gate pattern at the SSI level, and has the great feature that it does not require two masks as described in the first embodiment.

[Embodiment 5] This embodiment relates to a method of forming various gate lengths using a phase shifter according to the present invention. The smallest dimensions are obtained using only the edge portion of the phase shifter as described in the previous embodiments. In this case, when using an i-line (wavelength 365 nm) lens with a numerical aperture of 0.5, if the exposure amount is excessive, the minimum dimension will be 0.1
μm was also possible. A pattern having a cross-sectional structure of the glass substrate 71 shown in FIG. 13 is inserted into a mask for obtaining gradually thicker dimensions from such a minimum dimension. This is because one side of the phase shifter 73 is constructed on the Cr pattern 72. If the dimension L of the Cr pattern 72 of the 5:1 mask is made gradually thicker than 1.0 μm, the gate size on the wafer can be gradually increased from about 0.2 μm under the condition of excessive exposure. Can be done. This structure is also effective in improving the positional accuracy of fine patterns formed using edges. The positional accuracy of this pattern depends on the processing accuracy of the phase shifter. That is, if the pattern dimensions shift during the processing of the shifter, the center position of the fine pattern shifts by the amount of shift. Cr pattern 72
If the width of the phase shifter is made equal to the processing precision of the phase shifter, the shifter edge will always be located within the Cr pattern.
Deterioration in positional accuracy of the fine pattern to be transferred can be prevented. When forming a size of 0.6 μm or more using an i-line aligner, the phase shifter 73 having the configuration shown in the figure may or may not be used.

[Embodiment 6] Another embodiment of the present invention is shown in FIG.
This will be explained with reference to FIG.

This is an example of a pattern required to form source and drain regions by selectively growing GaAs with a high concentration, for example. FIG. 14 is a top view of the resist pattern, showing resists 200, 201 and an opening 202. In particular, the resist 201 in the center is required to have a dimension of 0.3 μm. FIG. 15 shows a mask structure for forming the resist pattern of FIG. 14. The Cr mask 302 has a window 303 through which light passes, and half of the window 303 is covered with a phase shifter 301. With this mask, a thin resist pattern can be formed at the edge of the phase shifter.

[Embodiment 7] Another embodiment of the present invention is shown in FIG.
This will be explained with reference to FIG.

This is a diagram showing an example of a mask pattern for obtaining two gate patterns in one FET with one mask, and the electrode arrangement of a GaAs MESFET manufactured using the same. When the gate electrode is formed by exposure using the Cr mask 402 and phase shifter 401 shown in FIG. 16, the Cr mask 402 and phase shifter 401 shown in FIG.
Pad portion electrodes 404 and F correspond to the edge portions of
The shapes of the ET gate electrodes 405 and 406 are obtained. In addition, source electrodes 407 and 408 and a drain electrode 409 are obtained by another process. This FET structure is used as a power unit that requires a low gate resistance and a long gate width, and a large number of these FETs are used to construct a power FET. The electrode 410 connecting the FET gate electrodes 405 and 406 has little to do with the performance of the FET, so it may be present or absent.

[0019]

[Effects of the Invention] The pattern forming method according to the present invention is effective for forming fine patterns having isolated patterns. Previously, 0
．． The resist pattern for gate processing of 3 μm or less was worked using an EB lithography system, and the processing time for a 3-inch wafer was about 30 minutes/piece. If the pattern forming method according to the present invention is used for this purpose, the same processing time will be less than 5 minutes per sheet, resulting in a significant reduction in time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing calculated values of light intensity distribution by a phase shifter of the present invention.

FIG. 2 is a diagram of a gate layer pattern of Example 1 of the present invention.

FIG. 3 is a configuration diagram of one mask used in Example 1 of the present invention.

FIG. 4 is a configuration diagram of the other mask used in Example 1 of the present invention.

FIG. 5 is a diagram of a resist gate pattern formed using the mask shown in FIG. 3 in Example 1 of the present invention.

FIG. 6 is a diagram of a desired resist gate pattern in Example 1 of the present invention.

FIG. 7 is a configuration diagram of one mask used in Example 2 of the present invention.

FIG. 8 is a configuration diagram of the other mask used in Example 2 of the present invention.

FIG. 9 is a diagram of a dual gate pattern of Example 3 of the present invention.

FIG. 10 is a side sectional view of a dual gate pattern according to Example 3 of the present invention.

FIG. 11 is a configuration diagram of a mask according to Example 4 of the present invention.

FIG. 12 is an explanatory diagram for obtaining a desired resist pattern by shifting the mask in Example 4 of the present invention.

FIG. 13 is a side sectional view of a mask pattern according to Example 5 of the present invention.

FIG. 14 is a resist pattern diagram of Example 6 of the present invention.

FIG. 15 is a diagram of a mask pattern used in Example 6 of the present invention.

FIG. 16 is a mask pattern diagram of Example 7 of the present invention.

FIG. 17 is a top view of the FET electrode of Example 7 of the present invention.

[Explanation of symbols]

13, 41, 42, 43, 63, 73, 91, 102,
301, 401---phase shifter, 12, 22, 44,
45, 46, 64, 65, 72, 92, 93, 402-
--Cr mask, 11, 21, 71, 10---Glass substrate, 32, 36, 37, 81, 82, 95---Resist pattern by phase shifter, 84---Semiconductor substrate crystal, 83--- gate metal.

Claims (7)

[Claims] [Claim 1] In the step of forming a pattern on a resist, the mask pattern is a mask composed of a pattern consisting of a light shielding part and a phase shifter part, and the mask pattern of minute dimensions formed on the resist is a mask formed by a pattern consisting of a light shielding part and a phase shifter part. A pattern forming method characterized in that the pattern is formed using at least one side of the pattern. 2. In the step of forming a pattern on the resist, the mask includes at least a pattern including a light shielding part and a phase shifter part, and a pattern for removing an unnecessary pattern formed by the pattern including the light shielding part and the phase shifter part. 2. The pattern forming method according to claim 1, wherein a desired resist pattern is formed by a composite image obtained from the mask. 3. The mask is composed of at least two masks, one mask has a pattern consisting of a light shielding part and a phase shifter part, and the other mask has an unnecessary pattern formed by the phase shifter part. Claim 1 obtained by a mask comprising a pattern for removing
The pattern formation method described. 4. The mask is composed of one mask, and the mask includes a pattern consisting of a light shielding portion and a phase shifter portion, and the mask includes a pattern including an unnecessary pattern formed by the phase shifter portion. 2. The pattern forming method according to claim 1, wherein the pattern for removing the pattern is obtained by a mask having a pattern formed at a predetermined position. 5. The pattern forming method according to claim 1, wherein the fine-sized mask pattern formed on the resist is formed using at least one side of the phase shift pattern. 6. The fine-sized mask pattern formed on the resist is formed using a portion where at least one side of the phase shift pattern and the light shielding pattern overlap.
The pattern formation method described. 7. The pattern forming method according to claim 1, wherein the mask pattern is used to form a resist pattern with minute dimensions in a manufacturing process of a compound semiconductor device.