JPH04340751A - Plastic molded type semiconductor device - Google Patents

Plastic molded type semiconductor device

Info

Publication number
JPH04340751A
JPH04340751A JP3112092A JP11209291A JPH04340751A JP H04340751 A JPH04340751 A JP H04340751A JP 3112092 A JP3112092 A JP 3112092A JP 11209291 A JP11209291 A JP 11209291A JP H04340751 A JPH04340751 A JP H04340751A
Authority
JP
Japan
Prior art keywords
semiconductor chip
chip
lead frame
resin
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3112092A
Other languages
Japanese (ja)
Inventor
Tetsuya Miyagaki
宮垣　哲也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP3112092A priority Critical patent/JPH04340751A/en
Publication of JPH04340751A publication Critical patent/JPH04340751A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent the warping of a package produced by the thermal shrinkage of a resin after the package is formed by sealing a semiconductor chip with the resin when the package is formed to a uniform thickness on the opposite sides of a lead frame on which the semiconductor chip is mounted by mounting a dummy semiconductor chip on the lower surface of the island section of the lead frame. CONSTITUTION:A dummy semiconductor chip 1 formed of the same material as that used for a semiconductor chip 2 to the same dimension as that of the chip 2 is mounted on the lower surface of the island section 3 of a lead frame, on the upper surface of which the chip 2 is mounted. For example, the chip 2 is mounted on the upper surface of the island section 3 of the lead frame by die bonding with a bonding agent 7 and the chip 2 is electrically connected with external terminals 5 with bonding wires 4. In addition, the dummy chip 1 is mounted on the lower surface of the island section 3 by similar die bonding. Then the chip 2 and 1 are sealed with a sealing resin 6 so that the thickness of the package can have a uniform thickness on the opposite sides of the lead frame.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【産業上の利用分野】本発明は樹脂封止型半導体装置に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.

【０００２】0002

【従来の技術】従来の樹脂封止型半導体装置は、リード
フレームのアイランド部の上面に半導体チップをダイボ
ンディングし、ボンディングワイヤにより、半導体チッ
プと外部端子との電気的接続を行ない、その後、樹脂封
止を行なうというものであった。この封止用樹脂は、リ
ードフレームを境としてパッケージの上下がほぼ対称と
なるように同一の厚さに形成されるのが一般的であった
。[Prior Art] In conventional resin-sealed semiconductor devices, a semiconductor chip is die-bonded to the top surface of an island portion of a lead frame, electrical connections are made between the semiconductor chip and external terminals using bonding wires, and then It was meant to be sealed. This sealing resin has generally been formed to have the same thickness so that the top and bottom of the package are approximately symmetrical with respect to the lead frame.

【０００３】0003

【発明が解決しようとする課題】上述した従来の樹脂封
止型半導体装置は、リードフレームの片面にのみ半導体
チップをダイボンディングにより搭載するため、リード
フレームを境としてパッケージの上下が同一の厚さに形
成する場合は上下の樹脂量が異なるので、樹脂封止後の
温度低下による封止用樹脂の熱収縮の差によりパッケー
ジが上面あるいは下面に反るという欠点があった。[Problems to be Solved by the Invention] In the conventional resin-sealed semiconductor device described above, the semiconductor chip is mounted only on one side of the lead frame by die bonding, so the top and bottom of the package with the lead frame as the border have the same thickness. In the case of forming a package, the amount of resin on the upper and lower sides is different, so there is a drawback that the package warps upward or downward due to the difference in thermal contraction of the sealing resin due to a temperature drop after resin sealing.

【０００４】0004

【課題を解決するための手段】本発明の樹脂封止型半導
体装置は、上面に半導体チップを搭載するリードフレー
ムのアイランド部の下面に搭載する前記半導体チップと
同一の材料を用い同一の寸法に形成した疑似半導体チッ
プを備えて構成されている。[Means for Solving the Problems] The resin-sealed semiconductor device of the present invention is made of the same material and has the same dimensions as the semiconductor chip mounted on the lower surface of the island portion of the lead frame on which the semiconductor chip is mounted. The device includes a pseudo-semiconductor chip formed therein.

【０００５】[0005]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

【０００６】図１は本発明の樹脂封止型半導体装置の一
実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of a resin-sealed semiconductor device of the present invention.

【０００７】本実施例の樹脂封止型半導体装置は、図１
に示すように、リードフレームのアイランド部３の上面
に半導体チップ２を接着剤７によりダイボンディングを
して搭載し、ボンディングワイヤ４により外部端子５と
電気的接続を行ない、アイランド部３の下面に疑似半導
体チップ１を半導体チップ２と同様なダイボンディング
により搭載し、封止用の樹脂６で樹脂封止を行なうもの
である。The resin-sealed semiconductor device of this example is shown in FIG.
As shown in FIG. 2, a semiconductor chip 2 is mounted on the top surface of the island portion 3 of the lead frame by die bonding with an adhesive 7, electrically connected to an external terminal 5 using a bonding wire 4, and a semiconductor chip 2 is mounted on the bottom surface of the island portion 3. A pseudo-semiconductor chip 1 is mounted by die bonding similar to the semiconductor chip 2, and resin-sealed with a sealing resin 6.

【０００８】疑似半導体チップ１は、半導体チップ２と
同一の材料、たとえば、シリコン単結晶を用いて同一の
寸法に形成したものである。これはたとえば、半導体チ
ップ２を形成するウエーハと同一のウエーハを用い半導
体チップ２と同一の寸法に切断したものである。あるい
は、半導体チップ２のチップ検査による不良品を用いて
もよい。The pseudo-semiconductor chip 1 is formed of the same material as the semiconductor chip 2, for example, silicon single crystal, and has the same dimensions. For example, the same wafer as the wafer forming the semiconductor chip 2 is used and cut into the same dimensions as the semiconductor chip 2. Alternatively, a defective product obtained by chip inspection of the semiconductor chip 2 may be used.

【０００９】[0009]

【発明の効果】以上説明したように、本発明の樹脂封止
型半導体装置は、上面に半導体チップを搭載するリード
フレームのアイランド部の下面に、半導体チップと同一
の材料を用い同一の寸法に形成した疑似半導体チップを
搭載するので、リードフレームを境としてパッケージの
上下が同一の厚さに形成する場合に上下の樹脂量は等し
くなるので、樹脂封止後の温度低下による封止用樹脂の
熱収縮の差によるパッケージの反りを防止することがで
きるという効果を有している。As explained above, in the resin-sealed semiconductor device of the present invention, the lower surface of the island portion of the lead frame on which the semiconductor chip is mounted is made of the same material as the semiconductor chip and has the same dimensions. Since the formed pseudo-semiconductor chip is mounted, if the top and bottom of the package are formed to the same thickness with the lead frame as the boundary, the amount of resin on the top and bottom will be equal, so the amount of resin used for encapsulation due to temperature drop after resin encapsulation will be reduced. This has the effect of preventing the package from warping due to differences in thermal contraction.

【図面の簡単な説明】[Brief explanation of drawings]

【図１】本発明の樹脂封止型半導体装置の一実施例を示
す断面図である。FIG. 1 is a sectional view showing an embodiment of a resin-sealed semiconductor device of the present invention.

【符号の説明】[Explanation of symbols]

１　　　　疑似半導体チップ ２　　　　半導体チップ ３　　　　アイランド部 ４　　　　ボンディングワイヤ ５　　　　外部端子 ６　　　　樹脂 ７　　　　接着剤 1 Pseudo semiconductor chip 2 Semiconductor chip 3 Island part 4 Bonding wire 5 External terminal 6 Resin 7 Adhesive

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　上面に半導体チップを搭載するリード
フレームのアイランド部の下面に搭載する前記半導体チ
ップと同一の材料を用い同一の寸法に形成した疑似半導
体チップを備えることを特徴とする樹脂封止型半導体装
置。1. A resin sealing method comprising a pseudo-semiconductor chip made of the same material and having the same dimensions as the semiconductor chip mounted on the lower surface of the island portion of the lead frame on which the semiconductor chip is mounted. type semiconductor device.
JP3112092A 1991-05-17 1991-05-17 Plastic molded type semiconductor device Pending JPH04340751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3112092A JPH04340751A (en) 1991-05-17 1991-05-17 Plastic molded type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3112092A JPH04340751A (en) 1991-05-17 1991-05-17 Plastic molded type semiconductor device

Publications (1)

Publication Number Publication Date
JPH04340751A true JPH04340751A (en) 1992-11-27

Family

ID=14577912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3112092A Pending JPH04340751A (en) 1991-05-17 1991-05-17 Plastic molded type semiconductor device

Country Status (1)

Country Link
JP (1) JPH04340751A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06295970A (en) * 1993-04-08 1994-10-21 Seiko Epson Corp Semiconductor device and manufacture of semiconductor device
KR20010066463A (en) * 1999-12-31 2001-07-11 박종섭 Stack package and the manufacturing method
JP2008172115A (en) * 2007-01-15 2008-07-24 Rohm Co Ltd Semiconductor device
US7622333B2 (en) 2006-08-04 2009-11-24 Stats Chippac Ltd. Integrated circuit package system for package stacking and manufacturing method thereof
US7645638B2 (en) 2006-08-04 2010-01-12 Stats Chippac Ltd. Stackable multi-chip package system with support structure
US7683467B2 (en) 2006-12-07 2010-03-23 Stats Chippac Ltd. Integrated circuit package system employing structural support

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06295970A (en) * 1993-04-08 1994-10-21 Seiko Epson Corp Semiconductor device and manufacture of semiconductor device
KR20010066463A (en) * 1999-12-31 2001-07-11 박종섭 Stack package and the manufacturing method
US7622333B2 (en) 2006-08-04 2009-11-24 Stats Chippac Ltd. Integrated circuit package system for package stacking and manufacturing method thereof
US7645638B2 (en) 2006-08-04 2010-01-12 Stats Chippac Ltd. Stackable multi-chip package system with support structure
US7915738B2 (en) 2006-08-04 2011-03-29 Stats Chippac Ltd. Stackable multi-chip package system with support structure
US8067272B2 (en) 2006-08-04 2011-11-29 Stats Chippac Ltd. Integrated circuit package system for package stacking and manufacturing method thereof
US7683467B2 (en) 2006-12-07 2010-03-23 Stats Chippac Ltd. Integrated circuit package system employing structural support
JP2008172115A (en) * 2007-01-15 2008-07-24 Rohm Co Ltd Semiconductor device

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