JPH04340809A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of a noise by dividing the transistor of an output buffer, controlling the change of an input signal to the output buffer, and suppressing rapid charge and discharge currents running through the entire output buffer. CONSTITUTION:When an input signal 2 of an output buffer circuit 52 is changed, a signal is transmitted to an input 5 of an output transistor 10, and an input 8 of an output transistor 12 in the same timing of the input signal 2, and the output of the output buffer is changed. At that time, a signal whose change is delayed by a fixed time from the input signal 2 by control circuits 17 and 18, is transmitted to an input 6 of an output transistor 11, and an input 9 of an output transistor 13. Thus, the currents running through an output 14 start running through the transistors 10 and 12 at first, and then they are increased by the transistors 11 and 13 after the delay of the fixed time. Therefore, the rapid current change at the output 14 can be suppressed.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit in a semiconductor integrated circuit comprising an insulated gate field effect transistor.

0002

2. Description of the Related Art A conventional output buffer circuit, as shown in FIG.
Transistors 48 and 49 connected in series and output circuit 4
An output buffer circuit 50 consisting of 7 is used to output to the outside.

0003

[Problems to be Solved by the Invention] In the conventional output buffer circuit described above, when the signal supplied to the outside from the output buffer circuit is at a high level, a large current flows from the output terminal 51, and when the signal is at a low level, A large current flows into the output terminal 51 from the output terminal 51. In that case, there are problems in that the internal current, ground, etc. fluctuate, causing malfunction of the internal circuit, and that a through current flows through the transistors 48 and 49, leading to an increase in power consumption.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output buffer circuit which solves the above-mentioned problems and prevents large currents from flowing in and out of output terminals.

[0005]

[Means for Solving the Problems] The configuration of the output buffer circuit of the present invention is such that first and second transistors are connected in series between first and second power supplies, and their common connection point is used as an output terminal.
third and third transistors in parallel with the first and second transistors, respectively;
The present invention is characterized in that a control circuit is provided which connects a fourth transistor, detects a change in an input signal, and controls transmission times of gate input signals of the third and fourth transistors, respectively.

[0006]

Embodiment FIG. 1 is a block diagram showing an output buffer circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of the control circuit 17 of FIG. 1, FIG. 3 is a circuit diagram of the control circuit 18 of FIG. 1, and FIG. 2 is a signal waveform diagram of each terminal in FIG. 1. FIG.

In FIG. 1, in this embodiment, the read operation of the memory device is performed when memory cell data is applied to terminal 1;
Reading is performed by the sense amplifier circuit 15 and a signal is sent to the output circuit 16. This output circuit 16 is a circuit that obtains waveforms at terminals 5 and 8 when the waveform at terminal 2 shown in FIG. 4 is applied. Also, terminal 7 is terminal 8, terminal 4
The respective inverted signals of terminal 5 are output. Further, the channel width of transistors 10 and 11 is half that of transistor 48, and the channel width of transistors 12 and 13 is half that of transistor 49.

For example, when a high-level signal is applied to terminal 2 of output circuit 16, a low-level signal is output to terminal 8, and transistor 12 is in an off state. A high level signal is output to terminal 7, terminal 21 is at high level, terminals 19 and 20 are at low level, transistors 23, 28, 29, and 30 are in an off state, and transistors 24, 25, 26, and 27 are in an off state. is in the on state, and the terminal 22 is at a low level. Therefore, the output 9 of the NOR gate (hereinafter referred to as NOR) 31 is at a low level, and the transistor 9, like the transistor 8, is turned off.

On the other hand, a low level signal is output to the terminal 5, and the transistor 10 is in an on state. In addition, a high level signal is input to terminal 4, terminal 34 is at high level, terminals 32 and 33 are at low level,
Transistors 38, 43, 44, and 45 are in an off state, transistors 39, 40, 41, and 42 are in an on state, and the terminal 25 is at a low level.

[0010] NAND gate (hereinafter referred to as NAND) 37 in FIG.
The signal at the terminal 35 is connected to one gate of the inverter 36.
A high level signal which is an inverted signal is inputted to the other gate, a high level signal at terminal 4 is inputted to the other gate, and a low level signal is outputted from terminal 6. Therefore, the transistor 11 is turned on like the transistor 10, and a high level is output to the output terminal 14.

When the signal at terminal 2 changes from high level to low level, terminal 5 changes from low level to high level, and transistor 10 is turned off. Also, the terminal 4 changes from high level to low level, and the NAND gate 27 in FIG.
The output of transistor 11 is inverted from a low level to a high level, and transistor 11 is turned off at approximately the same time as transistor 10. Furthermore, the signal at terminal 7 also changes from high level to low level, and the signal at terminal 8 also changes from low level to high level.
The transistor 12 is turned on.

At the time when the terminal 7 changes to a low level, the transistor 26 is turned off and the transistor 28 is turned on, and the terminal 22 changes from a low level to a high level, but the output 9 of the NOR gate 31 in FIG. The transistor 13 remains at a low level and remains off.

Next, the terminal 19 changes from a low level to a high level, turning off the transistor 24 and turning off the transistor 3.
0 is turned on. Next, the terminal 20 also changes from low level to high level with a delay of two inverters, transistor 27 turns off, transistor 29 turns on, and terminal 22 changes from high level to low level.

The NOR gate 25 is then inverted and the terminal 9
becomes high level, turning on transistor 13. In other words, there is a time difference due to the control circuit 17 when the transistors 12 and 13 turn on, which limits the current flowing from the output terminal and suppresses ground fluctuations.

In addition, when the output terminal changes from a low level to a high level, a similar operation is performed, and a time difference is provided for turning on transistors 10 and 11, so that the current flowing to the output terminal is It is possible to limit fluctuations in the power supply.

Further, the signal that turns off the transistors 12 and 13 when the output changes from a low level to a high level and the transistors 10 and 11 when the output changes from a high level to a low level is an input signal of the output circuit 16. Since the current changes by detecting changes in the current, the through current can be suppressed.

[0017]

As explained above, the present invention detects changes in the input signal of the output buffer circuit and suppresses the large current flowing at the time of output, thereby reducing fluctuations in the ground due to the internal current. This has the effect of preventing malfunction of internal circuits such as amplifiers, suppressing through current, and reducing current consumption.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of the first control circuit of FIG. 1;

FIG. 3 is a circuit diagram of a second control circuit of FIG. 1;

FIG. 4 is a signal waveform diagram of each terminal in FIG. 1;

FIG. 5 is a circuit diagram of a conventional output buffer circuit.

[Explanation of symbols]

1 Input terminals 3a, 3b, 3c Power terminals 14, 51 Output terminals 2, 4, 5, 6, 7, 8, 9, 19, 20, 21, 22
, 32, 33, 34, 35 terminals 10, 11, 2
3, 24, 27, 28, 38, 39, 42, 43, 48
P-type transistors 12, 13, 25, 26, 2
9, 30, 40, 41, 44, 45, 49 N-type transistor 15, 46 Sense amplifier circuit 16, 47 Output circuit 17, 18 Control circuit 50, 52 Output buffer circuit 31 NOR gate 36 Inverter 37 NAND gate

Claims (1)

[Claims] 1. First and second transistors are connected in series between the first and second power supplies, their common connection point is used as an output terminal, and third and second transistors are connected in parallel with the first and second transistors, respectively. An output buffer circuit comprising a control circuit connected to a fourth transistor and configured to detect a change in an input signal and control transmission times of gate input signals of the third and fourth transistors, respectively.