JPH0434169B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The present invention provides a system clock stretch circuit in a data processing device, and stretches the system clock based on a notified system clock delay signal during processing. By doing so,
The system clock cycle is extended when accessing low-speed devices.

[Industrial application field]

The present invention relates to a system clock stretch circuit configured to stretch a system clock supplied to a microprocessor or the like.

[Conventional technology]

Generally, when connecting devices or memory with slow access times to a system using a microprocessor, some types of microprocessors are equipped with terminals for inputting signals for use at low speeds. It can be operated by inputting a predetermined signal to the terminal. However, for devices without such terminals, for example, a circuit as shown in Figure 4 is used to generate a system clock with a slow cycle suitable for devices with slow access times. It was supplied to Setsa. The circuit shown in FIG. 4 will be explained below.

In FIG. 4, a clock oscillated by an oscillator 11 is supplied to phase change circuits 13 and 14, and two system clocks CLKQ and CLKE are generated at a predetermined phase, for example, with a phase delay of 1/4 clock cycle. It was generated and output. On this occasion,
Stretch circuits 15 and 12 operate based on instructions from stretch time generation circuit 16, which has preset constants to generate a system clock suitable for the slowest device connected to the system.
was controlled to generate and output system clocks CLKQ and CLKE extended by a predetermined clock amount.

[Problem that the invention seeks to solve]

The conventional circuit shown in FIG.
Since the CLKQ and CLKE cycles were set to occur at a fixed rate, if there were some devices with slow access times, the overall system clock cycle had to be slowed down, reducing throughput. There was a problem with putting it away.
Another problem is that it is necessary to set whether or not to slow down the system clock cycle depending on the availability of each system.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention includes a stretching circuit that generates an inverted signal in synchronization with the frequency-divided signal in a data processing device,
Based on the system clock delay signal notified during processing, the cycle is delayed and the system clock is expanded.

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, an oscillator 1 oscillates a clock using a crystal or the like.

The 1/2 frequency divider circuit 2 divides the frequency of the clock oscillated by the oscillator 1 to obtain a 50% duty.

Memory access signal/software setting signal circuit 3
holds an input signal C (system clock delay signal) notified by hardware or software when a memory or the like to which the system clock should be delayed is accessed.

The stretch circuit 4 generates a signal corresponding to an instruction from the memory access signal/soft setting signal circuit 3.

The clock phase changing circuits 5-1 and 5-2 generate two types of system clocks CLKQ and CLKE having different phases, for example, by 1/4 cycle.

[Effect]

When the configuration shown in FIG. 1 is adopted and the input signal C is input to the memory access signal/soft setting signal circuit 3, the memory access signal/soft setting signal circuit 3 controls the stretch circuit 4 to adjust the input signal C. is input, a signal delayed by a predetermined number of clocks is generated. These long-cycle signals delayed by a predetermined number of clocks are used to generate system clocks CLKQ and CLKE having a predetermined phase, for example, a phase difference of 1/4 cycle, by clock phase changing circuits 5-1 and 5-2. .

〔Example〕

Next, using FIG. 2 and FIG.
The configuration and operation of the embodiment will be explained in detail.

In Figure 2, oscillator 1 is a device that oscillates a clock using a crystal or the like, FF2-1 is a flip-flop that divides the clock frequency by 1/2 to generate a 50% duty signal, and FF3-1 constitutes a stretch circuit. FF4-1 is a flip-flop for determining whether to stretch or not, and FF5-3 and FF5-4 are flip-flops constituting a clock phase changing circuit.

Next, the operation of the configuration shown in FIG. 2 will be explained using the time chart shown in FIG.

In FIG. 3, the signal waveform of the clock generated by the oscillator 1 is shown.

The figure shows a signal waveform obtained by frequency-dividing the clock by FF2-1. Buffers connected between the oscillator 1 and the FF 2-1 and to the output end of the FF 2-1 buffer signals, respectively.

2 and 3 are system clocks CLKQ and CLKE respectively output from the output terminal Q of FF 5-3 and the output terminal Q of FF 5-4 in FIG. The signal (system clock CLKQ) is ahead of the signal (system clock CLKE) by 1/4 clock in phase. This corresponds to a two-phase system clock supplied to a microprocessor such as the MC6809E. The solid line portions in the time charts of the signals and the signals in FIG. 2 show the time charts when L level is supplied as the input signal (when the system clock is not delayed). In this case, FF in Figure 2
As shown in FIG. 2, an H level signal is supplied from the output terminal of FF 3-1 to the input terminal J of FF 4-1.
The signals shown by the solid lines in FIG. 3 are generated without delaying the cycles of the system clocks CLKQ and CLKE.

On the other hand, the H level is input as an input signal to FF3-1.
(when delaying the system clock), FF3-1 supplies a signal that is inverted depending on the signal to input terminal J of FF4-1.
The periods of the system clocks CLKQ and CLKE are extended as shown in the shaded areas in the time charts of FIG. This makes it possible to perform corresponding control even for devices with slow access times.

In addition, the input signal that delays the system clocks CLKQ and CLKE (system lock delay signal)
If a device with a slow access time is accessed, it should be detected by hardware and notified. Also, when an address exclusive to memory with slow access time, for example, any address from address 1000 to address 9000, is accessed,
This may be detected and notified by software.

〔Effect of the invention〕

As explained above, according to the present invention, the system clock is expanded during processing, so the system clock is expanded only when a device connected to the system with a slow access time is accessed. It becomes possible to delay the cycle of the lock, and the throughput of the entire system can be improved.

[Brief explanation of drawings]

FIG. 1 is a diagram of the principle of the present invention, FIG. 2 is a diagram of an embodiment of the present invention, FIG. 3 is a time chart of the configuration shown in FIG. 2, and FIG. 4 is an example of a conventional circuit. In the figure, 1 is an oscillator, 2 is a 1/2 frequency divider, 2-1,
3-1, 4-1, 5-3, 5-4 are flip-flops (FF), 3 is a memory access signal/soft setting signal circuit, 4 is a stretch circuit, 5-1, 5-
2 represents a clock phase changing circuit.

Claims (1)

[Scope of Claims] 1. In a data processing device that performs processing by incorporating a device with a slow access time into the system, a system clock stretch circuit configured to stretch a system clock supplied to a microprocessor is provided. , the system clock stretch circuit includes a frequency divider 2 that divides the frequency of the clock oscillated by the oscillator 1, and a frequency divider 2 that generates an inverted signal in synchronization with the frequency-divided signal by the frequency divider 2. Stretch circuit 4
and a clock phase changing circuit 5 that generates two types of system clocks by shifting the phase of the inverted signal inverted by the stretching circuit 4 by a predetermined amount. Based on the system clock delay signal, the period of the inverted signal inverted by the stretching circuit 4 is delayed to stretch the two types of system clocks output from the clock phase changing circuit 5. A system clock stretch circuit characterized by: