JPH0434181B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an instruction trace system for storing executed instructions, which is suitable for storing instructions executed by a digital computer, especially when it is not necessary to know the order of execution and the number of times of execution. Regarding equipment.

Recently, in order to improve the reliability of software programs, when all the test data prepared for the test is executed, the extent to which the execution of the paths in the program under test is shaded is measured.
Test sufficiency evaluation is performed, and if an instruction tracing device is used at that time, there is an advantage that the execution of the program under test is not affected.

Conventional instruction trace devices store all executed instructions or branch instructions in their execution order, so the number of instructions to be stored becomes enormous, requiring a storage device with a large storage capacity. The drawback was that the instruction trace period was limited to a relatively short period of time due to capacity limitations.

The purpose of the present invention is to solve this problem by
It is an object of the present invention to provide an instruction tracing device which requires only the use of a storage device having a small storage capacity and which can extend the period of instruction tracing.

In order to achieve such an objective, the present invention stores a specific number of most recently input pairs of branch instruction addresses and their branch addresses in a separate high-speed access storage device, and then stores them newly. A feature of this method is that when a pair of a branch instruction address and a branch destination address to be executed is stored in this storage device, it is not stored in the trace storage device.

In the present invention, when testing a program,
This is effective when detecting a path that has never been executed by using instruction tracing. In other words, instruction tracing is normally used to check the execution order of a program, so the execution order of branch instructions is important, but in the case of unexecuted path detection, it is only necessary to check whether or not execution has occurred; Applying the present invention is effective.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of an instruction tracing device according to the present invention. A conventional instruction trace device takes in data such as an instruction address, instruction type, and branch destination address regarding an instruction to be executed in a digital computer 1, selects only the branch instruction in a branch instruction selection unit 2, and stores the data in a trace memory. The control unit 5 repeats the operation of writing the pair of the instruction address and branch destination address of the branch instruction into the trace memory 6 through the trace memory control unit 5 every time an instruction is executed in the digital computer 1. When the data written in the memory 6 reaches a certain amount, the trace memory control section 5 writes the data to the external storage device 7.

The verification memory control section 3 and the high-speed accessible verification memory 4 in the instruction tracing device 100 shown in FIG. 1 are parts provided according to the present invention, and the verification memory control section 3 performs the following operations.

(1) Check whether the same pair of instruction address and branch destination address of the branch instruction selected by the branch instruction selection unit 2 exists in the verification memory 4;
If there is, this data is not sent to the trace memory control section 5. Therefore, this data is not written to the trace memory 6.

(2) If this data is not in the verification memory 4, write that data in the verification memory 4, and
It is sent to the trace memory control unit 5 and also written to the trace memory 6.

(3) In (2), when writing this data, if there is no free area in the verification memory 4, write this data in the area of the data that was written first among the data that has already been written. .

FIG. 2 shows a detailed flow of operations in the collation memory control section 3 of FIG. 1.

As shown in FIG. 2, first, in step 11, the starting address of the collation memory 4 is set in the search pointer sp. Next, in step 12, when a branch instruction is sent from the branch instruction selection unit 2, whether the input pair of branch instruction address and branch destination address is the same as the data in the collation memory 4 pointed to by the pointer sp. If they are the same, the process is terminated and data is not sent to the trace memory control unit.

On the other hand, if the input data is not the same as the data in the collation memory 4 pointed to by the pointer sp, in step 13, the length of one data is added to the pointer sp, and in step 14, the value is set at the end of the collation memory 4. It is checked whether it is larger than the tail address, and if it is not larger, the operations from step 12 described above are repeated. If the value of the pointer sp becomes larger than the last address of the collation memory 4, the process advances to step 15 and the input data is written in the area in the collation memory 4 pointed to by the write pointer wp. Next, in steps 16 and 17, the pointer wp is set to 1.
The length of the data is added, and the value is
If it is larger than the last address of wp, in step 18, the pointer wp is
The starting address of the collation memory 4 is set at .

In the above example, the comparison between the input data and the data in the verification memory 4 is performed up to the last address of the verification memory 4. Good too.

To explain a specific example of the operation of the present invention, consider a case where the following Fortran program is executed on the computer 1.

10 READ (5100) MAX 20 I=1 30 CONTINUE 40 I=I+1 50 IF (I.LE.MAX) GOTO30 60 STOP In this program, if IMAX is established by executing statement number 50, statement number 30 A branch occurs. Therefore, for example, if MAX is 100, the program execution order and statement numbers are 10 20 30 40 50100 times = 60.

When the embodiment of the present invention is applied to this, the following operation is performed.

(1) Since the statements with statement numbers 10, 20, 30, and 40 do not include branch instructions, they do not pass through the branch instruction selection unit 2.

(2) After statement number 50 passes through the branch instruction selection unit, the matching memory control unit 3 stores the pair of the address of statement number 50 and the address of statement number 30, which is the branch destination, in the matching memory 4, and The data is sent to the trace memory control section 5.

(3) When executing statement number 50 for the second time or later, the collation memory control unit 3 stores statement number 50 in the collation memory 4.
It is confirmed that the branch data from to statement number 30 is stored, and the data is not sent to the trace memory control unit 5.

(4) The trace memory control unit 5 stores the branch data sent from the verification memory control unit 3 in the trace memory 6.

As described above, in the conventional instruction trace device, the branch data from statement number 50 to statement number 30 is stored in the trace memory for the number of times it is actually executed (99 times in the above example), but in this embodiment, it is stored for only one time. It's over.

It should be noted that modifications of the embodiment of the present invention as shown in FIGS. 3 and 4 can be considered.

In FIG. 3, instead of the collation memory 4 in FIG. 1,
This is an example in which the trace memory 6 is also used. Normally, it is often necessary to use a verification memory 4 with a shorter access time than the trace memory 6 depending on its usage, but if this is not necessary, this method is possible.

FIG. 4 shows an example in which the trace memory 6 of FIG. 1 is not provided and data is written directly to the external storage device 7.
Normally, the time required to write to the external storage device is longer than the input interval of trace commands, so the trace memory 6 is used as a buffer, but if this is not the case, this method is possible.

As can be seen from the embodiments described above, according to the present invention, in most cases, data for only one branch instruction is collected instead of the conventional instruction tracing device that collects branch instruction data for the actual number of executions. As a result, trace memory usage efficiency can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an instruction tracing device according to the present invention, FIG. 2 is a flowchart showing an example of the operation of the verification memory control section of FIG. 1, and FIGS. FIG. 3 is a block diagram of another embodiment of the instruction tracing device according to the invention. 3...Memory control unit for verification, 4...Memory for verification, 6...Memory for tracing.

Claims (1)

[Scope of Claims] 1. A first memory means for storing at least one pair of data of a storage address and a branch destination address for each input branch instruction;
By searching the memory means of the first memory means, it is checked whether the pair data of the storage address of the newly input branch instruction and the branch destination address is stored in the first memory means, and the data is stored. and control means for obtaining the data as trace data only when the command is not being executed. 2 If the pair of data of the storage address of the newly input branch instruction and its branch destination address is not stored in the first memory means, and there is no free area in the first memory means; The instruction according to claim 1, characterized in that, in a certain case, data of a pair of the storage address of the newly input branch instruction and its branch destination address is written into the first memory means. tracing device. 3 In the case where the paired data of the storage address of the newly input branch instruction and its branch destination address is not stored in the first memory means, and there is no free area in the first memory means. If not, the pairing of the storage address of the newly input branch instruction and its branch destination address is stored in the area of the data written earliest among the data already written in the first memory means. 2. The instruction tracing device according to claim 1, wherein the instruction tracing device writes data. 4. The instruction tracing device according to claim 1, wherein a statement number or name written in a program is used as the storage address or branch destination address of the branch instruction. 5. The instruction trace according to claim 1, wherein a statement number or line number mechanically added to the program by an editor or compiler is used as the storage address and branch destination address of the branch instruction. Device.