JPH0434182B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for tracing input/output ports (hereinafter referred to as I/O ports) of a one-chip microprocessor in an in-circuit emulator.

[Prior Art] Many microprocessors have been developed in the past, and in-circuit emulators suitable for each microprocessor have been commercialized as development support devices. As a recent trend in microprocessors, single-chip microprocessors that incorporate not only central processing (hereinafter referred to as CPU) functions but also peripheral I/O functions are being actively developed.

[Problems to be Solved by the Invention] However, the conventional method has the following problems.

A 4-bit or 8-bit single-chip microprocessor is usually equipped with multiple general-purpose parallel I/O ports, but conventional in-circuit emulators mainly have bus tracing functions, so Currently, there is almost nothing to trace, including the state of

In addition, some boat circuit emulators realize I/O port tracing, but if you specify one port from multiple ports to trace, and the port of interest spans multiple ports. has no practical utility.

Furthermore, there are in-circuit emulators that connect probes for external logic tracing, but they have the disadvantage that it takes a lot of effort to connect the probes to the ports to be traced and to remove them when changing the trace ports.

Although it is originally desirable to trace all port data at the same time, it is necessary to expand the bit width of the trace memory by the number of bits of all ports. Therefore, it must be said that such simultaneous tracing of all port data is not very practical from the viewpoint of efficient memory usage.

The present invention solves these problems by allowing the user to specify the I/O port of interest within a certain set number, thereby expanding the trace memory bit width to a minimum. An object of the present invention is to provide an I/O port tracing method that can display the status of a designated I/O port for each bus cycle simultaneously with other bus traces.

[Means for solving the problems] In order to achieve such an object, the present invention has the following features:
Stores code that individually latches data on the bus line connected from each I/O port of the microprocessor installed in the in-circuit emulator to the target system into multiple data latches, and selects the I/O port bit. After the latching, the I/O port bit selection code is read by scanning the latched RAM at regular intervals, and based on this code, each bit is extracted from the latched port data and loaded into the shift register until the next bus cycle. Extract multiple bits of port data.

[Operation] All I/O port data is once latched in synchronization with the timing of sampling bus trace data in each bus cycle. Here, when extracting and tracing only the maximum m bits of port data,
A memory with a capacity m for storing a code for selecting an I/O port bit is prepared, and after latching, the addresses of this memory are automatically scanned at a constant cycle. An arbitrary bit is taken out from the port data latched in each cycle by the code data output from the memory.

By extracting m bits of port data by the trace sampling time of the next bus cycle, any specified I/O port data can be traced with a delay of one bus cycle.

[Example] The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of essential parts of an embodiment of a device for implementing the I/O port tracing method according to the present invention. In the figure, 1 is the incircuit.
This is a one-chip target microprocessor that is analyzed by the emulator. here,
Four sets of 8-bit general-purpose I/O ports (Pa, Pb,
A microprocessor with a built-in processor (Pc, Pd) is shown as an example. Each I/O port has bidirectional buffers 2a and 2 connected to I/O port buses B1 to B4 each having an 8-bit configuration.
It is connected to a target system (not shown) via lines b, 2c, and 2d.

Data latches 3a, 3b, 3c, and 3d are each individually connected to the I/O port buses Ba to Bd, and are used to latch all port data at that time in response to the trace sampling signal BUSCLK of each bus cycle. .

The bus lock BUSCLK is a signal related to the generation of a read signal (RD) or a write signal (WR) output from the microprocessor 1, and is generated at the gate 4.

5 is a 4-bit counter, which is a bus clock.
BUSCLK is used to count the scan clock SCANCLK with a constant period Tc. The scan clock is supplied from the system side.

The LSB (least significant bit) of the counter output is connected to the clock input of the shift register 9, and the upper 3 bits are used as an address when reading the register file 6.

The register file 6 is an 8-bit x 8-configured memory using RAM (random access memory), and allows the 5-bit code for selecting ports to be programmed for 8 ports arbitrarily from the system bus. be. This RAM
Write signal WR for 6, write address
WR-ADRS and write data WR-DATA
are both given from the system side. Upper 2 bits D3, D4 of data read from RAM
is sent to the decoder 7, which decodes it and outputs it to four data latches 3a, 3b, 3c,
3d, a signal that enables its output;
In other words, a latch output selection signal is generated.

The data selector 8 extracts only the specified bit from the 8-bit data output from the data latch and sends it to the shift register 9, based on the lower 3 bits D0, D1, and D2 of the output data given from the RAM. be.

The shift register 9 takes in the serial data input from the data selector 8 using the shift clock SFTCLK given from the counter 5.
The captured 8-bit parallel output is sent to the system side.

On the system side, this 8-bit data can be sampled and taken into the trace memory along with other bus information.

The operation in such a configuration will be explained next with reference to the time chart of FIG. The bus data of the I/O port bus output from the microprocessor 1 is sampled by the BUSCLK signal (b in Figure 2) generated by the gate 4, and each I/O port data is simultaneously sent to four data latches. 3a, 3b, 3c, and 3d. The counter 5 is also activated by this BUSCLK signal, and the period Tc shown in Fig. 2C is
SCANCLK counting starts. The upper three bits of the counter output are used as scan addresses A0, A1, and A2 of the register file 6 (FIG. 6(E)).

Therefore, from the register file 6, the port designation code PRi (i=0, 1,..., 7) represented by the read data output D0, D1, D2, D3, D4 is as follows.
As shown in FIG. 2, the signals are sent out sequentially at a cycle of 2·Tc.

The upper 2 bits of this output data D4, D3
is a latch selection signal, which is decoded by the decoder 7 to select one of the four latches.

On the other hand, the data selector 8 is connected to the register file 6.
The lower 3 bits of the data output from D2, D1,
Select one bit of the 8-bit output of the selected latch according to the value specified by D0,
This is sent to the shift register 9.

In short, 1-bit port data PNi (i=
0,1,. ．． ．． , 7) are sequentially input to the shift register 9. 8 pulse shift clock
Inside the shift register after SFTCLK occurs,
The port data of the eight types of ports programmed in RAM are arranged in order.

Therefore, by sampling this at the timing of the bus clock BUSCLK of the next bus cycle (N+1), it becomes possible to trace any I/O port. However, traced I/O port data is always delayed by one bus cycle from other bus trace data, so
Requires correction when displaying trace results. Also, if the minimum bus cycle time of this microprocessor is Tbmin, it is necessary to select Tc such that 8x2Tc<Tbmin, and if this specification cannot be secured due to delays such as RAM access time, wait (WAIT) state is selected. It is necessary to add a circuit for inserting the .

It goes without saying that the number of I/O ports, the number of data latches, etc. shown in the embodiments are not limited to these, and can be increased or decreased as desired. However, if there is an increase or decrease, it will be necessary to change each part accordingly, but such changes do not depart from the scope of the present invention.

[Effects of the Invention] As explained in detail above, according to the present invention,
To enable the user to extract and trace a certain number of port data that require tracing from among the many I/O ports provided in the microprocessor, we expanded the bit configuration of the trace memory. This has the advantage that it can be achieved with a simple software that displays trace results by only correcting bus cycles.

Furthermore, since the I/O port to be traced can be specified by command setting of the in-circuit emulator, more reliable and efficient setting is possible compared to the conventional method of connecting an external probe.

[Brief explanation of drawings]

FIG. 1 is a main part configuration diagram showing an embodiment of an apparatus for implementing the I/O port tracing method according to the present invention, and FIG. 2 is a time chart for explaining the operation. 1...Target microprocessor, 2
a, 2b, 2c, 2d...Batsuhua, 3a, 3
b, 3c, 3d...data latch, 4...gate, 5...counter, 6...register file,
7...Decoder, 8...Data selector, 9...
shift register.

Claims (1)

[Claims] 1. In an in-circuit emulator, data on a bus line connected from each I/O port of a microprocessor mounted in the in-circuit emulator to a target system is individually latched into a plurality of data latches. Then, after the latching, the memory in which the code for selecting the I/O port bits is stored is scanned at regular intervals to read out the I/O port bit selection code, and based on this code, one bit at a time is selected from the latched port data. By taking out the data, loading it into the shift register, and extracting multiple bits of port data by the next bus cycle, it is now possible to trace any specified I/O port data with a delay of one bus cycle. Characteristic I/O port tracing method.