JPH043431A - semiconductor equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an NPN transistor formed on a P-type semiconductor substrate, and in particular to an NPN transistor with good pulse response characteristics and a short accumulation time at saturation. The present invention relates to a semiconductor device including the present invention.

[Conventional technology]

A conventional NPN transistor formed on a P-type semiconductor substrate has a structure shown in a perspective cross-sectional view of FIG. That is, an N-type epitaxial layer 3 serving as a collector is formed on a P-type semiconductor substrate 1 having an N++ buried layer 2, and then an N+-type highly conductive path layer 7 is formed by selectively diffusing impurities from the surface of the N-type epitaxial layer 3. form. Next, a P-type isolation layer 4 is formed in a frame shape by selectively diffusing impurities from the surface of the N-type epitaxial layer 30. Next, a P+ type base layer 5 is formed in the N type epitaxial layer 3 surrounded by the P type isolation layer 4 and the substrate 1 by selective diffusion of impurities. Finally, an N+ type emitter layer 6 in the P+ type base layer 5 and an N++ collector contact layer 8 on the N+ highly conductive path layer 7 are simultaneously formed by selective diffusion of N type impurities.

[Problem to be solved by the invention]

When the above-mentioned conventional NPN transistor (Tr) formed on the P-type semiconductor substrate is saturated, the P+ type base layer 5 is the emitter, the N-type epitaxial layer 3 is the base, the P-type isolation layer 4 and the P-type semiconductor substrate 1. A parasitic PNP transistor (Tr) with collector Tr operates, and the NPNT
A part of the base current flowing into the base electrode of r is NPN
It flows into the P-type semiconductor substrate l via the N-type epitaxial layer 3 which is the collector layer of the Tr.

By the way, in the base current when NPNTr is saturated, the parasitic P
Due to N PTr, the proportion of current flowing through the N type epitaxial layer 3 to the P type semiconductor substrate 1 increases in proportion to the current amplification factor of the parasitic PNPTr. However, the NPs formed on the conventional P-type semiconductor substrate in the second section
In the NTr, a high concentration N+ buried layer 2 is formed between the P+ base layer 5, the P type child insulation layer 4, and the P type semiconductor substrate 1.
Because of the presence of the N+ high conductivity path layer 7, the current amplification factor of the parasitic PNPTr becomes small and the accumulation time of the NPNTr at saturation becomes long.

[Means to solve the problem]

In order to solve the above problems, in the semiconductor device of the present invention, between the P type substrate and the N+ National Institute of Technology conductor layer P+ base layer in the N type epitaxial layer surrounded by the isolation layer, there is a By providing a parasitic PNPTr collector layer connected to the P-type substrate 1 that just reaches the upper surface of the N+ buried layer, the current amplification factor of the parasitic PNPTr is increased, and the collector layer in the base current of the original NPNTr is increased. The amount of electron carriers injected into the base of the NPNTr is increased, thereby reducing the amount of storage and shortening the storage time.

〔Example〕

Next, the present invention will be explained by examples.

FIG. 1 is a perspective sectional view of an embodiment of the present invention.

In FIG. 1, N+
The upper surface of the substrate 1 on which the + buried layer 2 is formed and further includes the N+ buried layer 2 has an impurity concentration of 1015 to 1016 am-3.
N-type epitaxial layer 3 (NPNTr collector layer)
are piled up, and a P-type isolation layer 4 reaching from the top surface of the N-type epitaxial layer 3 to the substrate 1 is formed in a frame shape surrounding the N+ buried layer 2, and the P-type isolation layer 4 and the bottom P+ The N-type epitaxial layer 3 surrounded by the substrate 1 forms one unit element region. By selectively diffusing P-type impurities on the upper surface side biased to the right side of this element region, P
A + type base layer 5 is formed, and an N+ high conductivity path layer 7 is formed that reaches the N+ buried layer 2 from the top surface biased to the left side of the element region, and then an N4 type engineered layer is formed in the P+ base layer 5. 6, an N++ collector contact layer 8 is simultaneously formed on the upper surface of the N+ highly conductive path layer 7 by selective diffusion of N type impurities. The above is the same as the conventional NPN transistor shown in FIG. There is a P+ type parasitic PN at a depth just reaching the N+ buried layer 2 from the top surface of layer 3.
A PTr collector layer 9 is formed. This parasitic PNPTr collector layer 9 is connected to the same potential as the substrate l, and the existence of this collector layer 9 increases the current amplification factor of the parasitic PNPTr, and as a result, the original NPNTr
The accumulation time is shortened, and the pulse response characteristics are improved.

In the above embodiment, the parasitic PNPTr deflector layer is provided only on one side of the NPNTr base layer, but the parasitic PNPTr collector layer can be provided to surround the entire circumference of the P+ base layer.

〔Effect of the invention〕

As explained above, the present invention provides a P-type parasitic PNPTr collector layer having the same potential as the P-type semiconductor substrate between the P+-type base layer and the N+ high-conductivity path layer.
It is possible to increase the current amplification factor of the PTr and shorten the storage time when the NPNTr is saturated.

[Brief explanation of drawings]

FIG. 1 is a perspective sectional view of an example of the present invention, and FIG. 2 is a perspective sectional view of a conventional semiconductor device. 1...P+ semiconductor substrate, 2...N+ buried layer, 3...N-type epitaxial layer (NPNT
r collector layer), 4...P type isolation layer, 5...P+ base layer, 6...N+
Emitter layer, 7...N+highly conductive layer layer 8...
... Collector contact layer, 9 ... Parasitic PNP
Tr collector layer. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] An N-type layer is stacked on a P-type semiconductor substrate with an N^+ buried layer formed on the top surface side, and the N
A P-type isolation layer including the ^+ buried layer inside and reaching the P-type substrate is formed, and a P^+ base layer is formed in the element region surrounded by the substrate and the isolation layer.
An N^+ emitter layer is formed in the ^+ base layer, and an N^+ collector contact layer is further formed on the upper surface of the N type layer in the element region, and the N^+ collector contact layer and the N^+ buried layer are connected to each other. In a semiconductor device including an NPN transistor in which an N^+ highly conductive path layer is formed to connect the N-type layer to the N-type layer between the P^+ base layer and the N^+ highly conductive path layer from the top surface. A parasitic PNP transistor collector layer is formed with the P^+ base layer as the emitter, the N-type layer as the base, and the P-type substrate as the collector, with a depth just reaching the upper surface of the N^+ buried layer. A semiconductor device characterized by: