JPH0434329B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase detection circuit that detects a phase difference between two signals used for PLL control.

(Prior Art) Conventionally, this type of circuit consists of two signal detection circuits 16, 17 and a reset circuit 18 as shown in FIG. 5, and detects the arrival of two signals _R1 and _V1 . Detected reset signal (NAND gate 9
(output signal) to the two signal arrival detection outputs (added to NAND gates 2 and 8), respectively, to output phase detection outputs U ₁ and D ₁ .

(Problems to be Solved by the Invention) However, in such a configuration, the detection signal appears only at the output of the side where the signal arrived first, and if they arrive at the same time, the detection signal does not appear at either output.

Figure 2a shows the input signals R ₁ , V ₁ ,
Output signal and output signal U ₁ , D ₁ of NAND gate 9
This is an example of the waveform. In the figure, when the input signal R ₁ is slightly earlier than the input signal V ₁ as shown by the dotted line, the output signal U ₁ is output as shown by the dotted line, but when they arrive at the same time, the output signal U ₁ , D ₁ is not output.

Therefore, the phase detection characteristic in which the integral difference between two pulses is used as the phase detection output has the drawback that a dead zone appears near the phase difference of 0, as shown in a in FIG. 3, and the PLL control becomes unstable.

(Means for Solving the Problems) The present invention resets the two signal arrival detection outputs after sufficiently saturating them, and outputs the reset signal that detected the arrival of the two signals to the two signal arrival detection outputs. By not performing gate synthesis on any of them, the dead zone near the phase difference of 0 is eliminated, and the linearity of detection with respect to the phase difference is further improved. Embodiments of the present invention will be described in detail below with reference to the drawings.

(Example) Figure 1 shows an example of the present invention.
5, 6, 7, 8 and 9 are NAND gates, 10
is a delay circuit, R ₁ and V ₁ are input signals, and U ₁ and D ₁ are phase detection outputs.

NAND gates 1, 2, 3, and 4 constitute a signal detection circuit 11, NAND gates 5, 6, 7, and 8 constitute another signal detection circuit 12, and NAND gate 9 and delay circuit 10 constitute a reset circuit. It constitutes the circuit 13.

When the input signal _R1 is at H level, the output of NAND gate 1 goes to L level. Therefore, the output of NAND gate 3 goes to H level due to the operation of the SR flip-flop constituted by NAND gates 3 and 4, and the output of NAND gate 1 goes to H level. The output _U1 of 2 becomes H level.

Next, when the input signal _R1 becomes L level,
A signal is detected when the outputs of NAND gates 1 and 3 both go to H level. Also, at this time
The output _U1 of the NAND gate 2 changes to L level.

Similarly, when the input signal _V1 changes from H level to L level, the outputs of NAND gates 6 and 7 both go to H level, thereby detecting the signal. Also,
At this time, the output _D1 of the NAND gate 8 changes to L level.

With the arrival of the two L signals, the outputs of NAND gates 1, 3, 6, and 7 all become H level, so the NAND gate 9 of the reset circuit 13
The output of changes to L level, which is sent to delay circuit 10.
A reset operation is performed by delaying the signal and applying it to the NAND gates 4 and 5 via the common reset terminal A of the signal detection circuits 11 and 12.

The reset operation sets the outputs of NAND gates 3 and 6 to the L level, so the reset operation is canceled, and the outputs _U1 and _D1 of the NAND gates 2 and 8 both return to the H level.

To delay the reset signal, buffer circuits are connected in multiple stages, or a delay circuit using R and C (resistance capacitors) is used.

With this configuration, phase detection characteristics with good linearity and no dead zone can be obtained as shown in FIG. 3b.

Figure 2b shows the waveforms of the phase detection outputs _U1 and _D1 when the input signal _R1 arrives slightly earlier than the input signal _V1 , the output waveform of the NAND gate 9 for reset detection, and the reset signal waveform after the delay. It is what has appeared. The case where they arrive simultaneously is also shown, and in that case as well, the output signals U ₁ and D ₁ are output as shown by solid lines.

FIG. 4 shows another embodiment of the present invention, in which the reset signal for the circuit of FIG. 1 is generated by a NOR gate. Since the individual operations are well known, their explanation will be omitted.

(Effects of the Invention) As described above, according to the present invention, phase detection characteristics with no dead zone and good linearity can be obtained, so stable PLL control is possible.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
3 is an explanatory diagram of waveforms of each part, FIG. 3 is an explanatory diagram of detected output characteristics, FIG. 4 is another embodiment, and FIG. 5 is a conventional circuit diagram. 10... Delay circuit, 11, 12... Signal detection circuit, 13... Reset circuit.

Claims (1)

[Claims] 1. It has two signal detection circuits that detect and output the arrival of a signal, and a reset circuit that generates a reset signal in response to the arrival of a signal to both of the two signal detection circuits, and the two signal detection circuits In a phase detection circuit configured to repeatedly detect the arrival of two signals by resetting both signals, the reset circuit is provided with a delay circuit connected to a common reset terminal of the two signal detection circuits, and the delay circuit is connected to a common reset terminal of the two signal detection circuits. A phase detection circuit characterized in that the outputs of the two signal detection circuits are both made to sufficiently reach a saturation level by a reset signal that has passed through the phase detection circuit.