JPH04343473A - Ccd transfer circuit and ccd solid-state image pickup element - Google Patents

Abstract

PURPOSE:To ensure the removal of residual charges without changing a transfer speed or increasing it extremely by sweeping off the residual charges accumulated in the potential wells prepared at regular intervals on the way of CCD transfer route. CONSTITUTION:A CCD transfer circuit is formed on the surface of a p-type substrate. On the other hand, a CCD transfer route consists of a buried channel in which an n<-> layer is formed on the surface, and a transfer gate with two layers formed on the channel. Then two gates are paired and a transfer pulse H2 or H1 is commonly supplied, so that the electric potential gradient is generated. Furthermore, a residual charge sweeping section is prepared on the way of the CCD transfer route. The sweeping section for the residual charges is essentially equivalent in voltage to those of the output gate OG, reset MOSFETQ1 and reset gate pulse RG, and the reset voltage RD which are provided in the output section of the vertical CCD.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a CCD (charge-coupled device) transfer circuit and a CCD solid-state image sensor, and relates to a technique that is effective when used, for example, to remove residual charges in a CCD transfer path. .

0002

2. Description of the Related Art In an imaging device using a CCD, signal charges formed by photoelectric conversion by a photodiode are sent to a corresponding vertical CCD all at once via a PG gate.
The vertical CCD transfer operation and the horizontal CCD
Through the transfer operation, the signal is transmitted to the output diffusion layer through the OG gate and converted into a voltage signal, and the power is amplified by the amplifier circuit and output to the outside. An example of such an imaging device is ``1/2-inch IL-CCD with variable shutter function'' in the proceedings of the 1988 National Conference of the Television Society, p. 53.
There is a type element (1).

0003

Problems to be Solved by the Invention In a solid-state imaging device that transfers signal charges using a CCD, the transfer efficiency of the CCD influences the electrical characteristics of the solid-state imaging device. This transfer efficiency is determined by the signal charge generated in the photoelectric conversion section of the solid-state image sensor and the residual charge in the CCD transfer path that transfers the signal charge. In conventional CCD solid-state imaging devices, the residual charge mixes with the signal charge, resulting in a decrease in resolution and S/N (
The problem is that the signal-to-noise ratio (signal-to-noise ratio) deteriorates. An object of the present invention is to provide a CCD transfer circuit and a CCD solid-state image sensor that have a function of removing residual charges to the outside. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

0004

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, in a horizontal CCD transfer circuit that constitutes a CCD transfer circuit or a solid-state image sensor, potential wells are formed in which minute charges remain at regular intervals, and a non-operating period other than a signal charge transfer period or a horizontal retrace line is formed. A transfer operation is performed during the period to sweep out the charges accumulated in the potential well to the outside.

[0005]

[Operation] According to the above-mentioned means, the residual charges accumulated in the potential wells provided at regular intervals along the CCD transfer path are swept out, so the residual charges can be removed without changing the transfer speed or increasing it extremely. Exclusion can be ensured.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 5 shows a schematic circuit diagram of an embodiment of a CCD solid-state imaging device to which the present invention is applied. Each circuit in the figure is formed on a single semiconductor substrate such as single crystal silicon using a known semiconductor integrated circuit manufacturing technique. In the figure, in order to facilitate understanding of the entire CCD solid-state image sensing device, photodiodes D1 to D4 consisting of a total of four photodiodes D1 to D4 arranged in two rows and two columns are shown as a representative example. In reality, photodiodes are arranged in a matrix in multiple rows and columns, resulting in a total of about 200,000 to about 4
A large number of photodiodes, such as 00,000, are provided.

The anode side of the photodiode D1 is connected to the ground potential point of the circuit, and a photogate (hereinafter simply referred to as PG gate) is provided on the cathode side, and the photoelectrically converted signal charge is transferred to a vertical CCD (hereinafter referred to as VCCD). )'s V1
Transferred to gate. The other photodiode D2 in the same column is transferred to the V3 gate of VCCD via the PG gate. The photodiodes D3 and D4 in other rows are also PG in the same way as above.
The signal is transferred to the corresponding VCCD via the gate.

The signal charge at the final stage of VCCD is horizontal CC
D (hereinafter referred to as HCCD). The HCCD performs a charge transfer operation at high speed in synchronization with the transfer pulses H1 and H2 until the next signal charge is transferred from the VCCD, and converts the signal charge into a voltage signal using the detection capacitor C as described above. tell. OG provided at the output part of the HCCD is an output gate, and a bias voltage VG is supplied to the gate OG, which acts to smoothly transfer the signal charge of the HCCD to the detection capacitor C.

The signal charge transmitted to the detection capacitor C as described above is converted into a voltage signal and sent to the FDA (Floatin
The output terminal V is amplified by an amplifier called Diffusion Amplifier).
Sent from out. When the signal charge transferred to the detection capacitor C is output as a voltage signal through the amplifier Amp, it is reset pixel by pixel by the reset MOSFET Q1, in other words, it is swept out. RG is a reset gate pulse and RD is a reset voltage.

[0010] An outline of the signal charge readout operation of the CCD solid-state image pickup device will be described below. When the PG pulse is set to high level, the V1 gate and V3 gate of VCCD connected to the PG gate are set to high level. As a result, the photoelectric conversion charges of the photodiodes D1 and D2 (D3 and D4) are read out to the V1 and V3 gates of the VCCD. Next, for example, in an odd field, the V2 gate is set to high level. As a result, the signal charges under the V1 and V3 gates are mixed and once collected under the V2 gate. Thereafter, at the next timing, the V3 gate is set to high level, and at the next timing, the V4 gate is set to high level, and the signal charge is transferred downward. Thereafter, each gate is set to a high level in the order of V1 to V4, and the photoelectric conversion charge converted by the photodiode arranged above it is transferred in the same manner as described above.

Further, in an even field, V4 is set to high level instead of the V2 gate described above. As a result, the signal charges under the V3 and V1 gates are mixed by one row and are once collected under the V4 gate. Thereafter, at the next timing, the V1 gate is set to high level, and at the next timing, the V2 gate is set to high level, and the signal charge is transferred downward. In this way, by shifting the combination of signal charges by one row between odd and even fields, interlaced reading is equivalently performed.

FIG. 1 shows a potential distribution diagram for explaining the CCD transfer circuit according to the present invention, a residual charge sweep-out section provided therebetween, and its operation. FIG. 1A shows a schematic cross-sectional view of the element structure of a CCD transfer circuit and a residual charge sweeping section provided in the middle thereof. The CCD transfer circuit is formed on the surface of a p-type substrate (or a p-type well region formed on an n-type substrate). The transfer path of a CCD is composed of a buried channel having an n- layer formed on its surface, and a two-layer transfer gate formed thereon. A p-type impurity is introduced using the first layer gate as a mask to form an n- layer, and a second layer gate is formed on the n-layer so as to overlap with the first layer gate. . A potential gradient is created by making these two gates a pair and commonly supplying the transfer pulse H2 or H1. The second one is on the right side as shown in the same figure.
When a gate and an n- layer are provided, the potential potential on the left side becomes high (in the potential potential distribution diagrams (B) to (F) in the drawings, the potential increases toward the bottom),
Charge is transferred from the right side to the left side.

In this embodiment, a set of CCs as described above is used.
A residual charge sweeping section is provided in the middle of the D transfer path. This residual charge sweeping section is connected to the output gate OG and reset MOSFETQ provided at the output section of the HCCD.
1 and reset gate pulse RG and reset voltage RD
is substantially equivalent to That is, a gate formed similarly to the transfer gate is provided adjacent to the storage gate to which the transfer pulse H1 is supplied, and the bias voltage OG is applied thereto.
' is given. Although this voltage OG' is not particularly limited, it is set to a voltage corresponding to the high level of the transfer pulse H1. An n+ diffusion layer is provided between the gate and the transfer gate to which the transfer pulse H2 is supplied. This diffusion layer n+ is connected to a sweep reset voltage RD' via a switch MOSFET Q1' that receives a sweep timing pulse RG'.

[0014] The residual charge sweeping section as described above is an HC
They are provided at regular intervals in the middle of the CD. For example, when there are a total of 400 pixels in the horizontal direction, the HCCD is configured to perform a corresponding transfer operation for 400 bits. As shown in the timing diagram of FIG. 2, if a transfer operation for 10 bits is allowed to sweep out the residual charge during the horizontal retrace period B, every 10 bits are transferred as 400/10=40. A total of 40 residual charge sweeping sections are provided. As a result, all the residual charges in the HCCD can be swept out by ten transfer operations while keeping the frequency of the horizontal transfer clock unchanged. Note that when the timing signal CHD is at a high level, it is a signal readout period A, during which an output operation of 400 pixels corresponding to one scanning line is performed. In the horizontal retrace period B, several bits are provided as an output period for outputting optical black, so the entire horizontal retrace period B cannot be used for the transfer operation to sweep out the residual charge, and the NTSC system In this case, as mentioned above, there is a margin of about 10 bits.

FIG. 1B shows that during the scanning period in which the signal CHD is set to high level, the transfer pulse H1 is at high level, the transfer pulse H2 is at low level, as shown in the timing diagram of FIG. and timing pulse RG'
A potential distribution diagram of a normal transfer operation when is at a low level is shown. At this time, a transfer gate (second layer gate), an accumulation gate (first layer gate) corresponds to the low level of the transfer pulse H2, a transfer gate (second layer gate) corresponds to the high level of the transfer pulse H1, The potential potential increases in the order of the storage gate (first layer gate). Therefore, the signal charges are concentrated under the storage gate to which the transfer pulse H1 having the highest potential potential is supplied.

FIG. 1C shows that during the scanning period in which the signal CHD is set to high level, the transfer pulse H1 changes to low level and the transfer pulse H2 changes to high level, as shown in the timing diagram of FIG. In addition, a potential distribution diagram of a normal transfer operation when the timing pulse RG' is at a low level is shown. At this time, the transfer pulse H
In response to the change of H2 to high level and the change of transfer pulse H1 to low level, the highest potential portion moves to the left by half a bit, and correspondingly, the signal charge is transferred to the left. At this time, the gate OG', the n+ diffusion layer and the transfer pulse H2 forming the residual charge sweeping section
A shallow potential well is formed by the transfer gate to which the high level of is supplied, and signal charges are intentionally left behind. However, other signal charges except the first pixel are
The signal charge is mixed with the intentional residual charge that already exists before the transfer, but when the signal charge is transferred to the next stage, the intentional residual charge remains, so the signal charge is transferred as is.

In (D) of FIG. 1, during the horizontal retrace period when the signal CHD is set to a low level, the transfer pulse H1 is at a low level and the transfer pulse H2 is at a high level, as shown in the timing diagram of FIG. A potential distribution diagram is shown in which the timing pulse RG' changes and the timing pulse RG' is at a low level. At this time, similarly to (B) above, in response to the low level of the transfer pulse H2, the transfer gate (second layer gate), the storage gate (first layer gate), the transfer pulse H
Transfer gate (second layer gate) corresponding to the high level of 1
, the storage gate (first layer gate), the potential potential increases in this order. Therefore, the residual charges generated in the transfer operation during the scanning period are collected under the storage gate to which the transfer pulse H1 having the highest potential potential is supplied.

In (E) of FIG. 1, during the horizontal retrace period when the signal CHD is set to a low level, the transfer pulse H1 is set to a low level and the transfer pulse H2 is set to a high level, as shown in the timing diagram of FIG. A potential distribution diagram is shown when the timing pulse RG' is still at a low level. At this time, in response to the change of transfer pulse H2 to high level and the change of transfer pulse H1 to low level, the part with the highest potential moves to the left by half a bit, and correspondingly, the residual charge is transferred to the left. be done. At this time, the gate OG', the n+ diffusion layer, and the transfer pulse H that constitute the residual charge sweep-out section are
A shallow potential well is formed by the transfer gate to which the high level of 2 is supplied, and the residual charge can be kept there.

In (E) of FIG. 1, during the horizontal retrace period when the signal CHD is set to low level, the transfer pulse H1 is set to low level and the transfer pulse H2 is set to high level, as shown in the timing diagram of FIG. A potential distribution diagram is shown when the timing pulse RG is set to high level after the change. In response to the high level of the timing pulse RG', the MOSFET Q1' is turned on, and the residual charge trapped in the n+ diffusion layer is swept out by the reset voltage RD'. Thereafter, by similar transfer operations and the high level of the timing pulse RG, the n+
The residual charges transferred to the diffusion layer one after another can be sequentially swept out. Note that for the 10 bits on the output side of the HCCD, the output circuit also operates as a residual charge sweeping section. Therefore, during the horizontal blanking period, the timing pulse RG and the timing pulse RG' of the output circuit are the same timing pulse.

The effects obtained from the above embodiments are as follows. (1) In a horizontal CCD transfer circuit that constitutes a CCD transfer circuit or a solid-state image sensor, potential wells are formed in which minute charges remain at regular intervals, and during non-operation periods other than the signal charge transfer period or A transfer operation is performed during the horizontal retrace period to sweep out the charges accumulated in the potential well to the outside. With this configuration, even in a CCD transfer circuit consisting of multiple bits or a horizontal CCD, the residual charge accumulated in potential wells provided at regular intervals along the transfer path is swept out, so the transfer speed remains the same or is extremely high. The effect is that the residual charge can be reliably removed without having to do so. (2) Due to (1) above, it is possible to sweep out the residual charge for each horizontal scan, resulting in high resolution and high S.
The effect is that an output signal of /N can be obtained.

[0021] Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say. For example, when there are a total of 400 pixels in the horizontal direction, the frequency of the transfer clock for sweeping out the residual charge during the horizontal retrace period can be doubled to effectively perform the transfer operation for 20 pixels. For example, a total of 20 residual charge sweeping portions may be provided every 20 such as 400/10×2=20. However, if you do this,
Transfer for sweeping out residual charge during the horizontal retrace period,
It is necessary to switch the frequencies of the transfer clock pulses H1 and H2 between the output transfer of the optical black signal and the transfer during the scanning operation. In this way, the arrangement of the residual charge sweeping section can take various embodiments depending on the combination of the number of bits of the CCD transfer circuit, the time allowed for sweeping out the residual charge, and the frequency of the transfer clock at that time. .

[0022] The CCD transfer circuit is widely applied to not only the horizontal CCD in the CCD solid-state imaging device as described above, but also to CCD transfer circuits constituting line sensors, and various CCD transfer circuits used as analog shift registers, analog delay circuits, etc. It is something that can be done. CCD
The element structure of the transfer circuit may be of any type as long as it transfers the signal charge as described above in synchronization with a clock pulse. The element structure having a potential well for retaining residual charges may also be formed in consideration of the potential distribution during signal transfer. This invention can be widely used in CCD transfer circuits and CCD solid-state image sensors.

[0023]

Effects of the Invention A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, in a horizontal CCD transfer circuit constituting a CCD transfer circuit or a solid-state image sensor, a potential well is formed in which a small amount of charge remains at regular intervals, and during non-operating periods other than the signal charge transfer period or horizontally. A transfer operation is performed during the retrace period to flush out the charges accumulated in the potential well to the outside. With this configuration, even in a CCD transfer circuit consisting of multiple bits or a horizontal CCD, the residual charge accumulated in potential wells provided at regular intervals along the transfer path is swept out, so the transfer speed remains the same or is extremely high. This makes it possible to ensure that residual charges are removed without having to do so.

[Brief explanation of drawings]

FIG. 1 is a potential potential distribution diagram for explaining a CCD transfer circuit according to the present invention, a residual charge sweeping section provided in the middle thereof, and its operation.

FIG. 2 is an overall timing chart for explaining the operation of a CCD solid-state image sensor.

FIG. 3 is a timing chart of clock pulses for explaining a transfer operation during a scanning period among operations of a CCD solid-state image sensor.

FIG. 4 is a timing diagram of clock pulses for explaining a residual charge sweeping operation during a horizontal retrace period among operations of a CCD solid-state image sensor.

FIG. 5 is a schematic block diagram of a CCD solid-state image sensor to which the present invention is applied.

[Explanation of symbols]

H1, H2...Transfer clock pulse, RG...Reset pulse, RG'...Reset pulse for residual charge, VCCD...Vertical CCD, HCCD...Horizontal CCD, D1-D4...Photoelectric conversion element, Amp...Amplification circuit, C...Detection capacitor, Q1, Q1
'...MOSFET.

Claims (5)

[Claims] 1. Potential wells are formed in the middle of a CCD transfer path in which minute charges remain at regular intervals, and a transfer operation is performed during a non-operating period other than a signal charge transfer period to remove the charges accumulated in the potential wells. A CCD transfer circuit characterized by sweeping out the air to the outside. 2. The potential well includes a gate electrode substantially corresponding to the transfer gate, and a diffusion layer disposed in the transfer direction with respect to the gate electrode and having the same conductivity type as the transfer channel under the gate electrode, 2. The CCD transfer circuit according to claim 1, wherein a switch element is connected to said diffusion layer to sweep out signal charges remaining there. 3. A horizontal CCD that horizontally transfers the signal charge formed by the photoelectric conversion element, and a potential well is formed in the middle of the horizontal CCD transfer path so that minute charges remain at regular intervals. . A CCD solid-state image pickup device, characterized in that a horizontal CCD transfer operation is performed during a non-operating period other than a signal charge readout period to sweep out the charges accumulated in the potential well to the outside. 4. A vertical CCD that vertically transfers signal charges formed by a photoelectric conversion element;
A horizontal CCD receives the signal charge transferred by the horizontal CCD and transfers it in the horizontal direction, and a potential well is formed in the middle of the horizontal CCD transfer path so that minute charges remain at regular intervals, and during the horizontal retrace period. A CCD solid-state imaging device characterized in that a horizontal CCD transfer operation is performed to sweep out charges accumulated in the potential well to the outside. 5. The potential well includes a gate electrode substantially corresponding to the transfer gate, and a diffusion layer disposed in the transfer direction with respect to the gate electrode and having the same conductivity type as the transfer channel under the gate electrode, 5. The CCD solid-state imaging device according to claim 3, wherein a switch element is connected to said diffusion layer to sweep out signal charges remaining therein.