JPH04344714A - A/d converter - Google Patents

Abstract

PURPOSE:To provide an A/D converter in which the output timing of a data after A/D conversion and jitter in the AD conversion timing are considerably reduced. CONSTITUTION:A control variable and a frequency division ratio from a signal processing section are set to a control variable setting section 101 and a frequency division ratio setting section 103, a control signal representing addition/ subtraction/no control for fine-adjustment of the AD conversion timing is inputted to an addition/subtraction control section 102 and the conversion clock of an A/D converter section 105 is outputted from a variable frequency divider section 104. An A/D converter section 105 A/D-converts an analog data by using the clock and the result is tentatively buffered by a FIFO section 107 transferred to a P/S conversion section 109 and a data is outputted from a P/S conversion section 109 in the timing of the clock outputted based on the conversion clock of the variable frequency divider section 104, then jitter of the ADD-conversion timing is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AD converter capable of finely adjusting conversion timing, which is used when transmitting data through digital signal processing.

0002

2. Description of the Related Art Conventionally, an AD converter capable of finely adjusting conversion timing is configured as shown in FIG. 4, and a data demodulation system using this AD converter is configured as shown in FIG. has been done. The operation will be described below with reference to FIGS. 3 and 4.

First, in FIG. 3, the analog input AIN
An overview of the operation of demodulating analog data from 2 to digital data will be explained. Data from the analog input AIN is converted into digital data by the AD conversion section 302, and the digital data is sent to the signal processing section 301, where it is demodulated as received data by digital signal processing. Simultaneously with the demodulation of the received data, the timing clock DCLK of the received data is extracted, that is, the timing clock on the transmitting side is regenerated, and the signal processing unit 301 synchronizes with the phase of the regenerated timing clock.
From there, control is performed to the AD converter 302 to finely adjust the conversion timing.

[0004] Therefore, there is always a slight fluctuation in the timing of AD conversion, and the converted digital data is transferred to the signal processing section 301 in synchronization with the fluctuation. Normally, the signal processing unit 301 uses this transfer timing to create the reception data clock DCLK.
K is a clock that is synchronized with the timing clock on the transmitting side but contains jitter.

Next, a more detailed operation of the above-mentioned timing control will be explained with reference to FIG.

First, the supplied master clock MCLK
When the frequency of the conversion timing clock for AD conversion is 2.4576 MHz and the frequency of the conversion timing clock for AD conversion is 9600 Hz, “256” is set in the frequency division ratio setting unit 103 from the signal processing unit 301. Next, for example, “1” is input to the control amount setting section 101.
” is set and the AD conversion operation is started, parallel digital data is output from the AD conversion unit 105, and the data is passed through the P/S conversion unit 109 and converted to 1/960.
The signal is transferred to the signal processing unit 301 every 0 seconds. Then, the signal processing unit 301 reproduces the timing clock on the transmitting side from this digital data through digital signal processing, and the addition/subtraction control unit 10 reproduces the timing clock on the transmitting side in synchronization with the clock.
The AD conversion timing is finely adjusted by outputting a command to add to or subtract from 2, or to not control. For example, when adding or subtracting, the rate at which the AD conversion timing clock changes is ±1/256≒±0.
39, and if control is performed once every 1/9600 seconds, it is possible to follow a timing clock deviation of ±0.39%.

[0007]

[Problem to be Solved by the Invention] However, in the conventional example described above, the timing of AD conversion is finely adjusted, and the timing clock is regenerated from the converted digital data through signal processing to control the next conversion timing. As a result, a delay occurs between timing control and timing regeneration, and jitter occurs in the AD conversion timing after control. As a result, the timing clock of the received data created by the signal processing section also contains jitter, which causes problems in modulation and demodulation. In a system in which the data is repeated in a dependent manner, the jitter is accumulated and there is a high probability that the demodulated data on the terminal side will be erroneous.

The present invention has been made to solve the above-mentioned problems.
An object of the present invention is to provide an AD converter in which jitter in D conversion timing is significantly reduced.

[0009]

[Means to solve the problem] and

[Operation] In order to achieve the above object, the AD converter of the present invention has the following configuration.

That is, in an AD converter that finely adjusts the AD conversion timing of input analog data, a fine adjustment means finely adjusts the AD conversion timing of input analog data, and a conversion timing finely adjusted by the fine adjustment means. and a control means for controlling the timing of outputting AD-converted data based on the data, thereby reducing jitter components of the (received) data clock.

[0011] Furthermore, an AD converter according to another invention has the following configuration.

That is, in an AD converter that finely adjusts the AD conversion timing of input analog data, a fine adjustment means finely adjusts the AD conversion timing of input analog data, and a conversion timing finely adjusted by the fine adjustment means. and a control means for controlling a control signal input to the fine adjustment means based on the fine adjustment means, thereby suppressing jitter components of AD conversion timing.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a schematic block diagram showing the configuration of an AD converter in this embodiment. In the figure, reference numeral 101 denotes a control amount setting section, which is a register for setting the timing control amount (the number of increases and decreases in master clocks) in one cycle of AD conversion timing from the signal processing section. 102
1 is an addition/subtraction control section, which receives either addition, subtraction, or no control signal from the signal processing section, and performs addition/subtraction of the set value set in the control amount setting section 101. 103 is a frequency division ratio setting section, which is a register for setting the frequency division ratio of the variable frequency division section 104 from the signal processing section. 1
Reference numeral 04 denotes a variable frequency dividing section, which changes the setting value set in the frequency division ratio setting section 103 according to the control amount from the addition/subtraction control section 102 to perform frequency division of the master clock. 105 is A
This is a D conversion section, and performs AD conversion on data from the analog input AIN in synchronization with the output clock of the variable frequency division section 104.

106 is a PLL section, which includes a frequency division ratio setting section 1
03 and the output from the variable frequency divider 104, the output clock of the parallel/serial (P/S) converter 109, the details of which will be described later, is controlled. 107 is the FiFo section,
This is a memory for buffering digital data converted by the AD converter 105. 108 is a frequency dividing section, which outputs a shift clock to be input to the P/S converting section 109. 109 is a P/S converter that outputs serial data in synchronization with the clock from the frequency divider 108, but for each word of serial data, a PLL
The converted data is output in synchronization with the clock from section 106.

Next, the detailed configuration of the above-mentioned PLL section 106 will be explained with reference to FIG. 2. In the same figure, 201 is a phase comparator, which includes a variable frequency divider 104 and a variable frequency divider 20.
Compare the clock phase with 7. A frequency dividing section 202 divides the output of the variable frequency dividing section 207. 203 is a frequency division control section, and based on the result of the phase comparison section 201, the variable frequency division section 2
Outputs a signal that controls the frequency division ratio of 07. A flip-flop 204 outputs, together with a NOR circuit 205, a signal that is turned on for one cycle of the output of the variable frequency divider 207 every time the output from the frequency divider 202 falls. 206
is a mask control section, which outputs a frequency division control signal from the frequency division control section 203 in accordance with a signal from the NOR circuit 205. 207 is a variable frequency dividing section, and the frequency dividing ratio setting section 1
The set value from 03 and the frequency division control signal from the mask control unit 206 are input, and a clock obtained by dividing the master clock is output.

Timing control of the AD converter in the above configuration will be explained below.

First, in the configuration shown in FIG. 3 described above, when demodulating data, the operation of the signal processing section 301 is the same as in the conventional example. In other words, set the master clock to 2.45
76MHz, AD conversion timing clock 9600MHz
Hz, the frequency division ratio setting unit 103 in FIG.
” is set. As a result, the variable frequency dividers 104 and 20
7 is normally a 256 frequency divider circuit and outputs 9600Hz. Further, "1" is set in the control amount setting section 101. With this setting, AD conversion is performed in the AD converter 105 at the clock timing output from the variable frequency divider 104, digital data is output, and the F
The data is input to the memory of the iFo unit 107 and temporarily buffered. The FiFo section 107 is the P/S conversion section 10
When the output of data 9 is completed, the oldest stored data is output to the P/S converter 109. The timing of this data output depends on the timing of the clock output from the PLL section 106. Further, the frequency of the master clock is divided by, for example, 4 by the frequency dividing unit 108, and then the P/S converting unit 109
Used as a shift clock for data output from The output data of the P/S converter 109 is subjected to digital signal processing by a signal processor, the data is demodulated, and the timing clock on the transmitting side is regenerated. In order to synchronize with the phase of the reproduced clock, an instruction for addition, subtraction, or no control is given to the addition/subtraction control section 102, and the frequency division ratio of the variable frequency division circuit 104 is set to "255" to "257".
”. At the AD conversion timing changed by adjusting the frequency division ratio, the signal processing unit performs signal processing for timing reproduction using the converted digital data. This signal processing includes: Since a delay normally occurs, the clock of the variable frequency divider 104 that controls the AD conversion timing contains jitter.The output of the variable frequency divider 104 containing this jitter is input to the PLL unit 106, At step 201, the phase is compared with the clock output from the variable frequency divider 207.

Note that since the variable frequency dividing section 207 has already been set to divide by "256" by the setting of the frequency dividing ratio setting section 103, the output of the variable frequency dividing section 104 and the variable frequency dividing section 2 are initially set.
The outputs of 07 are synchronous. However, if a lead/lag occurs in the output of the variable frequency divider 104 due to control from the signal processor, the phase comparator 201 outputs the phase difference. The frequency division control unit 203 determines whether the output clock is ahead or behind a certain level (for example, ±π/8),
In order to cancel this, the frequency division ratio of the variable frequency division section 207 is set to "2".
A control signal for changing to "55" or "257" is output.

In addition, the frequency dividing section 202 divides the output of the variable frequency dividing section 207 (for example, by dividing the frequency by 8), and uses the flip-flop 204 and the NOR circuit 205 to divide the output of the variable frequency dividing section 207.
O for one cycle of the output of 207 every time the output of 2 falls.
A signal equal to N is output. That is, a signal that turns ON only once every eight cycles is output and input to the mask control section 206. In the mask control section 206, the frequency division control signal of the frequency division control section 203 described above is turned on when the output of the NOR circuit 205 is turned on.
Since the signal is passed only when , even if the control signal is output every cycle, the frequency is divided by only 1/8.

That is, ±1/256×1/8≒±0.
049% is the maximum control amount.

[0022] With the control explained above, all jitter due to AD conversion timing within ±1/8π is absorbed, and even for jitter beyond that, 1/1/1 of the control amount is absorbed by the signal processing section.
Suppressed by 8. Further, the difference between the AD conversion timing and the data output timing is absorbed by the FiFo memory 107.

As explained above, according to this embodiment,
By providing an AD converter that can finely adjust the conversion timing with means for absorbing jitter in the conversion timing and means for outputting digital data after AD conversion at the timing at which the jitter has been absorbed, the timing of AD conversion can be improved. Even in a system where modulation and demodulation are repeated dependently even if jitter occurs in the received data clock, data errors due to accumulation of jitter in the received data clock can be significantly reduced.

[0024]

[Other Embodiments] Next, other embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a schematic block diagram showing the configuration of an AD converter in another embodiment. In this embodiment, a jitter suppression section 110 is provided before the addition/subtraction control section 102 to reduce jitter due to delay in signal processing. Components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and the explanation here will be omitted.

As shown in the figure, the jitter suppressor 110 includes:
Based on the AD conversion clock frequency-divided by the variable frequency divider 104, a command to add or subtract the frequency division ratio inputted from the signal processing unit, or to not control it, is output to the addition/subtraction control unit 102.

Next, the jitter suppressor 1 in this embodiment
The detailed configuration of 10 will be explained with reference to FIG. In the figure, 601 is a frequency dividing section, which inputs the conversion timing clock from the variable frequency dividing section 104 and outputs a clock divided by eight, for example. 602 is a flip-flop;
Together with the NOR circuit 603, each time the output from the frequency divider 601 falls, the voltage is output for one cycle of the output from the variable frequency divider 104.
Outputs a signal that becomes N. A mask control unit 604 outputs an addition/subtraction control signal according to a signal from the NOR circuit 205.

In the above configuration, the frequency dividing section 601 has an AD
When the output from the variable frequency divider 104, which is a conversion timing clock, is input, the clock is frequency-divided by eight, for example, and output to the flip-flop 602 and the NOR circuit 603. The output of the NOR circuit 603 turns ON for one cycle of the output of the variable frequency divider 104 from the fall of the output of the frequency divider 601. That is, even if the addition/subtraction control signal is input to the mask control section 604 at every AD conversion timing, the output of the mask control section 604 is controlled only 1/8 times.

Therefore, using the AD-converted digital data, the signal processing section regenerates the timing clock on the transmitting side through digital signal processing, and controls the timing of AD conversion so as to be synchronized with the phase of the clock, thereby suppressing jitter. A control signal is input to section 110, and this control amount includes jitter due to signal processing delay. However, as described above, this jitter is controlled by the jitter suppressing section 110 to approximately 1/8 the number of times of control, the jitter component is also suppressed, and the jitter in the output timing of digital data after AD conversion is also reduced. That is, even if the signal processing section operates at the converted data output timing output from the AD converter and generates the reception data clock at that timing, timing with suppressed jitter can be obtained.

As explained above, according to another embodiment, an AD converter capable of finely adjusting the conversion timing is provided with means for suppressing the jitter of the timing clock after conversion timing control. Even if rough timing control is performed in the signal processing section of a demodulation system using signal processing, it is possible to reduce the jitter of the timing clock of received data. This has the effect of significantly reducing the probability of data errors due to accumulation.

Note that the frequency division ratio of the frequency division section in the embodiment is "8".
For example, it may be configured so that it can be set externally and made variable instead of being fixed to ``.

The present invention may be applied to a system made up of a plurality of devices, or to a device made up of one device. It goes without saying that the present invention can also be applied to cases where the present invention is achieved by supplying a program to a system or device.

[0033]

[Effects of the Invention] As explained above, according to the present invention,
It is possible to significantly reduce jitter in data output timing or AD conversion timing after AD conversion.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing the configuration of an AD converter in this embodiment.

FIG. 2 is a diagram showing a detailed configuration of a PLL section in this embodiment.

FIG. 3 is a diagram showing the configuration of a general demodulation system.

FIG. 4 is a schematic block diagram showing the configuration of a general AD converter.

FIG. 5 is a schematic block diagram showing the configuration of an AD converter in another embodiment.

FIG. 6 is a diagram showing a detailed configuration of a jitter suppression section in another embodiment.

Claims (2)

[Claims] 1. An AD converter that finely adjusts the AD conversion timing of input analog data, comprising a fine adjustment means for finely adjusting the AD conversion timing of input analog data, and a conversion timing finely adjusted by the fine adjustment means. control means for controlling the timing of outputting the AD-converted data based on the control means, and reducing the jitter component of the output timing of the AD-converted data.
D converter. 2. An AD converter that finely adjusts the AD conversion timing of input analog data, comprising: a fine adjustment means that finely adjusts the AD conversion timing of the input analog data, and a conversion timing that is finely adjusted by the fine adjustment means. an AD converter, comprising: control means for controlling a control signal input to the fine adjustment means based on the fine adjustment means, and suppressing jitter components of AD conversion timing.