JPH0434475Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an electronic watch with an alarm function.

[Prior art]

In recent years, electronic watches equipped with large-capacity memories have been developed, and by storing telephone numbers, schedules, etc. in this memory, they are also used as telephone directories and notebooks. In an electronic watch having such a data memory function, when displaying a schedule, for example, if the schedule is displayed all at once, each character will be displayed small because the size of the display section is limited. Therefore, in such a display method, the larger the number of characters in the schedule, the smaller each character becomes, making it harder to see.
Therefore, it has been proposed to display the characters by a sweep display method in which the characters flow in one direction. According to this sweep display method, each character can be made larger, making it very easy to read.

[Problems with conventional technology]

By the way, when a schedule or the like is stored in a memory, the data in the memory is converted into display data and stored in a display RAM, and one bit of data in this RAM is stored in correspondence to one dot on the display section.
For example, a liquid crystal display element is used as the display section. When performing a sweep display as described above, the data stored in the RAM is shifted sequentially in one direction on the RAM, or the data stored in the RAM is
By rewriting the contents so that they are shifted, the characters are displayed in a flowing manner. but,
In such a sweep display method, when the number of dots increases or the sweep speed increases, the sweep process requires a corresponding amount of time. Therefore, when an alarm sounds during the sweep process, the control section of the watch requires time to perform the sweep process, so there is a problem that the alarm does not sound properly and the alarm sound is disturbed.

[Purpose of invention]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide an electronic timepiece that can make an alarm sound normally under any circumstances.

[Key points of the idea]

In order to achieve the above object, the present invention is such that when the alarm time is reached during a sweep display, the sweep display is forcibly stopped so that an alarm sound is normally sounded.

[Example of idea]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes an oscillator that generates a clock signal of a predetermined frequency using a crystal resonator, and the clock signal generated by the oscillator 1 is sent to a frequency dividing circuit 2 and a timing generator 3. . The frequency dividing circuit 2 divides the frequency of the clock signal sent from the oscillator 1 to generate a constant cycle time measurement signal, a buzzer drive signal for sounding a buzzer, and the like. The time measurement signal is used for time measurement processing, which will be described later, and the buzzer drive signal is sent to the buzzer drive section 17 and used to generate a buzzer sound. The timing generator 3 divides the clock signal sent from the oscillator 1 into a constant frequency, outputs a timing signal for controlling each block in time series, and is also a chip for controlling access to RAM4 and RAM5.・Enable signal (CE4, CE
5). The RAM 4 is a small-capacity random access memory (RAM) that stores frequently accessed data such as clock data such as the current time and control data. On the other hand, RAM
5 is a large capacity random access memory (RAM) that stores data bank data such as telephone numbers and schedules.

Access to the RAM 4 and RAM 5 becomes possible when the chip enable signal (CE) becomes "H" (high level), and this control is performed by the timing generator 3 as described above. The key input unit 6 includes a data input unit for inputting data for the switches S ₁ and S ₂ and the data bank, and inputs key input signals related to the operated switches S ₁ and S ₂ to the ROM address control unit 7. At the same time, the data input from the data input section is stored in a working register or the like inside the RAM 4.

The ROM address control section 7 creates an address for the ROM 8 based on the key input signal, and supplies the address to the ROM 8. The ROM 8 is a read only memory that stores microprograms and data that control the entire electronic watch, and based on the address sent from the ROM address control unit 7, it executes micro instructions RA and D. , OP, and NA are output in parallel. Microinstruction RA is an address signal for RAM 4, and is input to RAM 4 via data bus A.

When the microinstruction RA is input, the RAM 4 outputs data at the address specified by the microinstruction RA to the display buffer 10, multiplexer 12, RAM 5, etc., which will be described later. Microinstruction D is data information such as alphanumeric data and address information of RAM 5, and is transmitted via data bus B to RAM 5,
RAM address control unit 18 and multiplexer 1
2 is output. Further, the microinstruction OP is an operation code, and is sent to the control section 13 via the data bus C. Control part 1
3, when the microinstruction OP is input, the control signal a is generated based on the operation code.
The control signals b and c are output to the ROM address control unit 7 to control the ROM address control unit 7.
is output to the timing generator 3. Also,
Various control signals are also output to each of the other blocks.

The timing generator 3 receives control signals b, c
The chip enable signal CE4, described above based on
Generates timing control signals to be supplied to CE5 and each block.

The microinstruction NA is the next address data of the microprogram stored in the ROM 8, and is output to the ROM address control unit 7.
It is again supplied to the ROM 8 via the ROM address control section 7.

The multiplexer 12 selects the data sent via the data bus A based on a control signal (not shown) sent from the timing generator 3 or the control section 13, and selects the data sent via the data bus D.
It is output to the arithmetic circuit 14 via the data bus E or to the register 15 via the data bus E. The register 15 outputs the temporarily stored data to the arithmetic circuit 14 via the data bus F in synchronization with the data output from the multiplexer 12 via the data bus B. The arithmetic circuit 14 connects the multiplexer 12 and register 1 via data buses D and F, respectively.
Arithmetic and logical operations are performed on the data input from 5, and processed data obtained from the results is output to a predetermined register of RAM 4 via data bus G.

The address counter 16 is stored in RAM for alarm detection processing that compares the current time and alarm time.
This is an address addition circuit of RAM 4 used in the process of accessing multiple data of concatenated addresses of ROM 4. It adds the address value of microinstruction RA input from ROM 8 via data bus A, and adds the address value of microinstruction RA input from ROM 8 via data bus A. Output to ROM8. The RAM address control unit 18 is a circuit that controls the address of the RAM 5, and supplies an address to the RAM 5 based on the microinstruction D sent from the ROM 8. And the buzzer drive section 17
is a circuit for inputting a buzzer drive signal of a predetermined frequency from the frequency dividing circuit 2 via the data bus G and generating a buzzer sound based on the control signal d also sent from the frequency dividing circuit 2. .

Furthermore, when a telephone number is stored in the RAM 5, a person's name and the corresponding telephone number are stored, but when the data of this telephone number is displayed on the display section 11, it is displayed using a sweep display method.
When performing this sweep display, the display mode is changed by the switch _S1 of the key input section 6, and a command signal is sent from the control section 13 to the timing generator 3 based on this key instruction.
This allows timing generator 3 to
A chip enable signal (high level) is sent to the RAM 5, and the data selected by the switch _S2 of the key input section 6 is temporarily transferred from the RAM 5 to the RAM 5.
Transferred to 4. The data transferred to the RAM 4 is sent to the display buffer 10, where the data is sequentially shifted and sent to the display section 11. As a result, data is displayed flowing in one direction on the display unit 11, and a sweep display is executed. Note that if the current time coincides with the set alarm time during this sweep display, the sweep display is forcibly stopped, as will be described later.

FIG. 2 is a flowchart showing the operation of the embodiment. Hereinafter, the operation of the present invention will be explained with reference to the same figure.

First, in step _a1 it is determined whether or not a key operation has been performed, and if there is a key instruction, in step _a2 it is determined whether the key instruction is switch _S1 . switch
S ₁ is a switch for changing the display mode,
Each time this switch _S1 is pressed, the display mode changes cyclically. Therefore, if switch _S1 is pressed, the _above -mentioned
The display mode is switched by adding 1 to the mode register M provided in the RAM 4. Also, Switch S ₁
Each time the key is pressed, 1 is added to the mode register M at step _a3 , so the display mode is switched as described above. On the other hand, if the switch _S1 has not been pressed at step _a2 , the process advances to step _a4 , and it is determined whether the switch _S2 has been pressed. Switch on step a ₄
If _S2 is pressed, it is determined in step _a5 whether the content of mode register M is 1 or not, and if it is 1, page register P provided in RAM4 is determined in step _a6 .
Performs processing to add 1 to . That is, when M=1, the data bank display mode is selected as the display mode, and each time switch _S2 is pressed, 1 is added to the page register P to change the displayed page. Switch.

In this embodiment, there are three display modes: time display mode, data bank display mode, and alarm time display mode.As shown in Fig. 3, the display mode changes cyclically each time switch _S1 is pressed. It is starting to switch to . Furthermore, when the data bank display mode is selected, the display page changes each time the switch _S2 is pressed. The data bank display mode is
It displays the data stored in the RAM 5 in a sweep display, for example, a person's name and the corresponding telephone number. Also, step a ₅
If M is not 1, process another switch _S2 in step _a7 , and if switch _S2 is not pressed in step _a4 , process another key in step _a5 . .

On the other hand, if there is no key instruction at step _a1 , it is determined at step _a9 whether or not a 16 Hz clock signal is output from the frequency dividing circuit 2. That is, a 16 Hz clock signal is output from the frequency dividing circuit 2, and the process proceeds to step _a10 every 1/16 seconds when this clock signal is output. Step _a10 is to determine whether or not the alarm flag F provided in the RAM 4 is 1, and F=1.
When this happens, the buzzer is already sounding.
Therefore, if the set alarm time has not been reached, F=0, so proceed to step _a11 .
The system will wait until the current time matches the alarm time. Then, when the current time and alarm time match in step _a11 , the alarm flag F is set to 1 in step _a12 , and the counter C provided in RAM4 is cleared, and in the same way.
The sound alarm time flag E in RAM4 is set to 1 and the timer T is started. The counter C and the sound time flag E are used to set the sound time and stop time of the buzzer to 1/4 second, respectively, and to perform a process of switching the time alternately. Next, in step _a13 , the sound latch is set, the buzzer starts sounding, and the process advances to step _a14 . step
A ₁₄ performs time measurement processing using the 16 Hz time measurement signal from the frequency dividing circuit 2, and the time measurement data obtained by this processing is stored in the time register of the RAM 4. Further, in step _a15 , as described above, the display is performed in the display mode selected by the switches _S1 and _S2 , and this display process will be described later with reference to the flowchart of FIG.

After the alarm starts, return to step a ₁ again, and step
Step a ₁₀ after the 16Hz clock signal is output at step a ₉
Proceed to. At step _a10 , since the alarm flag F was set to 1 at step _a12 , F
= 1, so we proceed to step _a16 . At step _a16 , 1 is added to the counter C, and the process proceeds to step _a17 . step
Step _a17 is for determining whether the content of counter C is 4 or not. Here, since 1 was only written in step _a16 , C=1. Therefore, by adding 1 to the counter C at step _a16 every 1/16 seconds, the process proceeds to step _a18 after C=4.
If 1/16 seconds is counted four times, it becomes 1/4 second, so proceed to step _a18 after 1/4 second has elapsed since the start of the warning sound. At step _a18 , it is determined whether or not the alarm time flag E is 1. Here, since the alarm time flag E was set to 1 at step _a12 , E=1. Then E=1
Therefore, proceed to step _a19 , reset the alarm latch, clear counter C, and press E.
Set to 0 to stop the buzzer.
As a result, the buzzer sound will temporarily stop after 1/4 second,
At step _a20 , it is determined whether or not the timer T has elapsed for 10 seconds. At this stage, only 1/4 second has elapsed since the timer T started, so step _a20 becomes NO and the process returns to step _a1 again. Then, in the same way as above, 1 is added to the counter C every 1/16 seconds at step _a16 , and when C=4 (after 1/4 second has elapsed), the process proceeds to step _a18 , and it is determined whether E=1 or not. Determine. In this case, the sound alarm time flag E is set to 0 as described above, so (a ₁₉ ), E=0
Therefore, proceed to step _a21 . In step a ₂₁ ,
The alarm latch is set, the alarm time flag E is set to 1, the flag E is set to 1, and the alarm by the buzzer is started again. Therefore, after 1/4 second has elapsed since the warning sound was stopped, the warning sound is started again.
Note that in step _a21 , counter C is also cleared.

In this way, the alarm sound and the alarm stop are repeated alternately every 1/4 second, and at step _a20 , the timer T is
After 10 seconds have been counted, the alarm flag F and the alarm time flag E are each set to 0 in step _a22 , and the alarm processing is ended.

FIG. 4 shows a detailed flowchart of the display processing.

In FIG. 4, first, in step _b1 , it is determined whether the contents of the mode register M are 1 or not. As explained in FIG. 3, when M=0, the time display mode is selected by the switch _S1 . That's when it happened. In this case, time display processing for displaying the current time is performed in step _b2 . If M=0 is not found in step _b1 , the process proceeds to step _b3 , where it is determined whether M=2 or not. When M=2, the data bank display mode is selected as the display mode, and
Proceeding to step _b4 , it is determined whether the alarm flag F is 1 or not. When F=1, as mentioned above,
This is when a 10-second alarm process is in progress, and in this case, in step _b5 , processing is performed to forcibly stop the sweep display of the data bank display. This results in
If the current time coincides with the set alarm time during the sweep display, the sweep display is forcibly stopped, so the alarm sound can be sounded without any disturbance. Note that this stopping operation is performed until the warning sound ends, and the timer T
counts 10 seconds and when F=0, the original sweep display process is started again. Further, when F=0 in step _b4 , the data of the P page selected by switch _S2 is displayed in a sweep display in step _b6 . Furthermore, if M=2 is not determined in step _b3 , the remaining display mode 1 (M=1) is selected, and in this case, the set alarm time is displayed.

[Effect of idea]

As explained above, according to the present invention, the sweep display is forcibly stopped when the current time matches the set alarm time during the sweep display, so the alarm sound is disturbed as in the conventional method. This problem can be solved and the alarm sound can be generated normally.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the embodiment, FIG. 3 is an explanatory diagram showing the display mode switching state, and FIG. 4 is a flowchart showing the main operations of the present invention. 2... Frequency divider circuit, 3... Timing generator, 4... RAM (small capacity), 5... RAM (large capacity), 6... Key input section, 8... ROM, 11...
...Display section, 13...Control section, 17...Buzzer drive section.

Claims (1)

[Scope of utility model registration request] A timekeeping means for obtaining current time information by timing a reference signal, a display means for displaying the current time information obtained by the timekeeping means, and storing information different from the current time information obtained by the timekeeping means. an information storage means, a sweep display control means for causing the display means to sweep display information different from the current time information stored in the information storage means, and an alarm time storage means for storing alarm time information;
an alarm flag register in which a flag is set when the current time information obtained by the timer matches the alarm time information stored in the alarm time storage means, and the flag is reset after a predetermined period of time has elapsed; Alarm sound generation means generates an alarm sound while the flag is set in the alarm flag register, and information different from the current time information is displayed in a sweep manner on the display means by the sweep display control means. determining means for determining whether or not a flag is set in the alarm flag register; and stopping the sweep display by the sweep display control means when the determining means determines that the flag is set. and a sweep display stop/start control means for restarting the sweep display by the sweep display control means when the discrimination means determines that the flag is not set after the stop. A distinctive electronic clock.