JPH04344770A - Image processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus that binarizes pixel signals read by a scanner or the like.

0002

2. Description of the Related Art Recently, in the information society, there are an increasing number of devices that handle image data. Devices that handle such image data require an image processing device that converts pixel data read by a scanner or the like into a binary image signal. Furthermore, recently, image processing apparatuses handle not only black and white binary images such as characters, but also halftone images such as photographs. Documents containing such halftone images include not only halftone images but also
Binary images are often mixed, and in order to perform binarization processing on images of originals that contain such binary images and halftone images, it is necessary to accurately separate the binary image area and the halftone image area. It is necessary to perform appropriate binarization processing on both image areas.

Conventionally, when reading a document with a halftone image, the signal level difference between a pixel of interest and an adjacent pixel is detected, and if the signal level difference is larger than a predetermined value, the sign of the signal level difference is Based on this, the white or black of the pixel of interest is determined. Furthermore, as described in Japanese Patent Application Laid-Open No. 62-149263, in the case of an image of a document containing a mixture of binary images and halftone images, a two-dimensional image filter is set around the pixel of interest. The filter coefficients of the two-dimensional image filter are time-divisionally switched within the image signal transfer time of one pixel, and the outputs of the plurality of filters are compared with each other.
Value image areas and halftone image areas are identified.

Conventionally, as described in Japanese Patent Application Laid-Open No. 61-251273, an edge enhancement correction coefficient is set for each difference data between a pixel of interest and edge correction data for each adjacent peripheral pixel, and natural The image quality of the output image is improved by performing contour enhancement processing, and furthermore,
As described in Publication No. 48380, peak binarization processing and differential binarization processing are performed in parallel for each line of input image data, and the logical sum of these binarized data is output as a binary value. By outputting the data as converted data, missing data is compensated for by the peak binarized data, and a binarized image that is faithful to the original image is output.

[0005]

[Problems to be Solved by the Invention] However, with such conventional image processing devices, it is not possible to accurately determine the edges of white and black, and the image processing apparatus cannot accurately determine the edges of white and black. There are problems in that distortion occurs in the image, lines become thicker or thinner, and high-speed processing circuits are required, making the image processing apparatus expensive.

[0006] Furthermore, in the method described in Japanese Patent Laid-Open No. 149263/1983, arithmetic processing is performed by switching a plurality of filters in a time-sharing manner within the image signal transfer time of one pixel, and the filters are By comparing the calculation results with each other,
Since the binary image area and the halftone image area are determined, a high-speed processing circuit is required, which raises the cost of the image processing device and, by extension, the cost of the facsimile machine that uses the image processing device. .

[0007]Furthermore, in the method described in Japanese Patent Application Laid-open No. 61-251273, the memory capacity for setting the edge enhancement correction coefficient is large, so a facsimile machine that similarly uses an image processing device However, in the method described in Japanese Unexamined Patent Publication No. 63-148380, the differential circuit converts the differential binary value within the peak binary processing time of the image signal of one pixel. Since the image processing is performed in parallel, a high-speed differential processing circuit is required, which again poses the problem of increasing the cost of facsimile machines and the like that utilize the image processing device.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an image processing device that realizes a binarization circuit that appropriately binarizes images in which binary images and halftone images are mixed, with a simple hardware configuration. shall be.

[0009]

[Means for solving the problem] The invention according to claim 1 includes:
In an image processing device that binarizes a multi-value pixel signal input for each line based on a predetermined reference value for each pixel and outputs an output binary pixel signal, the level of the pixel of interest of the input multi-value pixel signal A matrix forming means for forming and outputting matrix data indicating the levels of adjacent pixels at the same position in the lines before and after the pixel of interest, and correcting the matrix data using a predetermined correction filter and outputting the corrected matrix data. a smoothing means for smoothing the matrix data and outputting smoothed matrix data; and a smoothing means for smoothing the matrix data and outputting smoothed matrix data; fixed binarization means for outputting a converted pixel signal; and a fixed binarization means for outputting a multi-step binary pixel signal by comparing the pixel level of interest in the matrix data with a multi-step reference value that changes in multiple steps and performing binarization processing. a second multi-stage binarization means for performing binarization processing by comparing the pixel level of interest in the smoothed matrix data with a multi-stage reference value that changes in multiple stages, and outputting a multi-stage binarized image signal; a multi-stage binarization means; an image area determination means for comparing the level of the pixel of interest in the correction matrix data with a predetermined area determination value to determine whether the pixel of interest is a character image area or a halftone image area; a halftone dot area determining means for determining whether the pixel of interest is in a halftone image area by comparing the difference between the pixel level of interest and the level of the pixel of interest in smooth matrix data with a predetermined reference value; Based on the determination result of the means, one of the binarized image signals of the fixed binarization means, the first multi-stage binarization means, and the second multi-stage binarization means is selected to output the binarized image. selection means for outputting the fixed binary image signal as a signal, and when the input pixel signal is in a character image area, the selection means selects the fixed binary image signal output from the fixed binary conversion means as the output binary image signal. When the input pixel signal is in a halftone image area, the multi-stage binarized image signal outputted by the first multi-stage binarizing means is selected and outputted as the output binarized image signal, and the input pixel signal is When the signal is in a halftone image area, the multi-stage binarized image signal outputted by the second multi-stage binarized means is selected and outputted as the output binarized image signal, as claimed in claim 2. The described invention provides an image processing device that binarizes a multi-value pixel signal input for each line based on a predetermined reference value for each pixel and outputs an output binary pixel signal. Matrix forming means for forming and outputting matrix data indicating the level of a pixel of interest and the level of adjacent pixel signals at the same position on lines before and after the pixel of interest, and correcting the matrix data using a predetermined correction filter. correct the level of the pixel of interest, compare the level of the pixel of interest with a predetermined fixed reference value, and perform binarization processing;
A correction binarization means outputs a fixed binary pixel signal, and a binarization process is performed by comparing the pixel level of interest in the matrix data with a multi-step reference value that changes in multiple steps to generate a multi-step binary pixel signal. Multi-stage binarization means for outputting and weighting the matrix data using a predetermined weighting filter, extracting an edge pixel level of a pixel of interest, and comparing the edge pixel level with a predetermined reference value to perform binarization processing. , an edge extracting means for outputting an edge binary image signal, and a character region determining means for comparing the level of the pixel of interest in the matrix data with a predetermined character image region determination value to determine whether the pixel of interest is in the character image region; When the edge extraction means extracts an edge pixel, it compares each surrounding pixel of the extracted matrix data with a predetermined density determination reference value, and based on the comparison result, each surrounding pixel that becomes the background of the edge pixel is ambient density comparison means for identifying a level difference between the pixel of interest and the pixel of interest, when the pixel of interest is a character image area, selects a fixed binary pixel signal of the correction binarization means and outputs it as an output binary image signal; , selection means for selecting a binary image signal from either the multi-stage binarization means or the edge extraction means based on the identification result of the ambient density comparison means and outputting the selected binary image signal as an output binary image signal; When the input pixel signal is in the character image area, the selection means selects and outputs the fixed binary pixel signal output from the correction binarization means as the output binary pixel signal, and the input pixel signal is in the halftone image area. In this case, when the ambient density comparison means identifies that the level difference between the pixel of interest as an edge pixel and all surrounding pixels is less than a predetermined value, the selection means selects the multi-stage 2 output from the multi-stage binarization means. When the digitized image signal is selected and outputted as an output binary image signal, and the surrounding density comparison means identifies that at least one of the pixel of interest as an edge pixel and the surrounding pixels is larger than a predetermined value, the selection means selects and outputs the digitized image signal. The invention according to claim 3 is characterized in that the edge binary image signal outputted by the edge extracting means is selected and outputted as the output binary image signal, is a halftone image area, when the surrounding density comparison means identifies that the level difference between the pixel of interest as an edge pixel and all surrounding pixels is less than a predetermined value, the selection means outputs the output from the edge extraction means. The present invention is characterized in that the edge binary image signal is selected and output as the output binary image signal, and edge pixels in the halftone image area are output.

0010

[Operation] In the invention as claimed in claim 1, matrix data is formed from the input pixel signal, an image area is determined from the pixel level of interest in the matrix data, and when the input pixel signal is a character image area, it is fixed by the selection means. A fixed binary image signal based on the correction matrix data outputted by the binarizing means is selected and output as an output binary image signal,
When the input pixel signal is in a halftone image area, the first multi-stage 2
When the multi-level binary image signal based on the smoothed matrix data output by the value conversion means is selected and output as the output binary image signal, and the input pixel signal is in the halftone image area,
A multi-stage binary image signal based on the matrix data outputted by the second multi-stage binarizing means is selected as an output binary image signal and output.

Therefore, without using an expensive high-speed processing circuit, character image areas, halftone image areas, and halftone image areas of a document image containing a mixture of binary images and halftone images can be appropriately and quickly processed. This makes it possible to reduce the cost of the image processing device, as well as to appropriately perform binarization processing of pixel signals in the binary image area, halftone image area, and halftone image area, and to It is possible to prevent lines from becoming thinner or thicker, and image quality can be improved.

In the invention according to claim 2, matrix data is formed from the input pixel signal, an image area is determined from the pixel level of interest in the matrix data, and when the input pixel signal is a character image area, the selection means performs correction. 2
Fixation 2 based on the correction matrix data output by the value conversion means
When the digitized image signal is selected and output as the output binary image signal and the input pixel signal is in a halftone image area, the ambient density comparison means calculates the level difference between the pixel of interest as an edge pixel and all surrounding pixels. is identified as being less than a predetermined value,
The selection means selects and outputs a multi-stage binarized image signal based on the matrix data output from the multi-stage binarization means as an output binarized image signal, and the surrounding density comparison means compares the target pixel as an edge pixel and the surrounding pixels. When at least one of them is identified as being larger than a predetermined value, the selection means selects the edge binary image signal output from the edge extraction means as output 2.
It is selected and output as a digitized image signal, and claim 3
In the described invention, when the input pixel signal is in a halftone image area, when the ambient density comparison means identifies that the level difference between the pixel of interest as an edge pixel and all surrounding pixels is less than a predetermined value, the selection is performed. The edge binary image signal output from the edge extracting means is selected and output as an output binary image signal by the means, and edge pixels in the halftone image area are emphasized.

Therefore, without using an expensive high-speed processing circuit, it is possible to appropriately and quickly identify the character image area, halftone image area, and edge image area of a document image containing a mixture of binary images and halftone images. This makes it possible to reduce the cost of the image processing device, and also to reduce the number of pixel signals in the binary image area, halftone image area, and edge image area.
By appropriately performing value conversion processing, it is possible to prevent lines from becoming thinner or thicker, and image quality can be improved. Also,
A high contrast image can be obtained by emphasizing edge components in a halftone image area.

[0014]

EXAMPLES The present invention will be specifically explained below based on examples. 1 to 11 are diagrams showing an embodiment of a scanner device to which an image processing device according to the first aspect of the invention is applied. FIG. 1 is a diagram showing the appearance of a scanner device 1. The scanner device 1 includes an image reading mechanism and an image processing mechanism for processing read image data, which will be described later, in a main body 2. , ADF (Auto Document Feed) serves as a document table 3 on which a book document can be set and an automatic document feed mechanism on which a plurality of sheet documents can be set.
er) unit 4 is provided, and sheet originals discharged from the ADF unit 4 are placed on a paper discharge table 5.

FIG. 2 is a block diagram of a schematic configuration of an image reading mechanism and an image processing mechanism stored in the main body 2 of FIG. , a memory 9, an I/F processing section 10, and the like. The image reading unit 6 is composed of a line image sensor and its peripheral circuits, and optically reads the original image set on the original table 3 or the ADF unit 4 line by line and outputs analog image data to the shading processing unit 7. do.

The shading processing section 7 is composed of a line memory, an AD converter, a peak hold circuit, etc., and performs shading processing on the analog image data inputted from the image reading section 6, and binarizes it as digital multilevel image data. It is output to the arithmetic processing section 8. Binarization calculation processing unit 8
As shown in FIG. 3, the matrix forming circuit 11, MT
F correction circuit 12, smoothing circuit 13, fixed threshold binarization circuit 14, dither processing circuit A 15, dither processing circuit B
16, a comparator A17, a comparator B18, a subtraction circuit 19, a comparator C20, a block area determination circuit 21, a timing delay circuit 22, and a selection circuit 23.

The matrix forming circuit (matrix forming means) 11 is composed of a line buffer and a latch that forms a two-dimensional space centered on a pixel of interest of input digital multivalued image data (multivalued pixel signal). , two-dimensional matrix data is formed that indicates the density level of the pixel of interest and the density levels of the surrounding pixels on the front, rear, left, and right sides adjacent to the pixel of interest. For example, as shown in FIGS.
Alternatively, by forming 3×3 matrix data, the MTF correction calculation circuit 12, the smoothing circuit 13, and the dither processing circuit B
Output to 17.

MTF (Modulation Tran)
sfer Function) The correction calculation circuit (correction means) 12 performs filter calculation processing on the matrix data inputted from the matrix forming circuit 11 using a predetermined correction filter, that is, performs correction processing on the blurred image, and performs MTF-corrected attention. The pixel data is output to the fixed threshold binarization circuit 14, comparator B17, comparator C18, and subtraction circuit 19.

The smoothing circuit (smoothing means) 13 performs smoothing processing based on the relationship between the pixel of interest and surrounding pixels in the matrix data inputted from the matrix forming circuit 11, that is, averages the pixel density levels to form a read image. The halftone dot image in the center is reproduced without moiré, and the smoothed pixel data of interest is output to the dither processing circuit A15 and the subtraction circuit 19.

The fixed threshold binarization circuit (fixed binarization means) 14 receives M
The TF corrected pixel data of interest is compared with a predetermined fixed threshold value (fixed reference value), binarized, and output to the timing delay circuit 22 as fixed binarized image data. The dither processing circuit A (second multi-stage binarization means) 15 compares the smoothed pixel data of interest inputted from the smoothing circuit 13 with a threshold value (multi-stage reference value) set in a predetermined multi-stage. The data is then binarized and output to the timing delay circuit 22 as multi-stage binarized image data.

The dither processing circuit B (first multi-stage binarization means) 16 converts the pixel data of interest inputted from the matrix forming circuit 11 into threshold values (multi-stage reference values) set in predetermined multiple stages. The data are compared, binarized, and output to the timing delay circuit 22 as multi-stage binarized image data. The comparator B17 compares the MTF corrected pixel data of interest inputted from the MTF correction calculation circuit 12 with a predetermined setting threshold value B, and the comparator C18 compares the MTF corrected pixel data of interest inputted from the MTF correction calculation circuit 12 with a predetermined threshold value B. The image density level of the pixel of interest was compared with the set threshold value C, that is, the threshold values B and C are set to determine the pixel density as shown in FIG. The comparison result is output to the block area determination circuit 21. In FIG. 6, threshold values B and C (area discrimination values) are set to determine whether the pixel of interest is a character image area or a halftone image area.

The subtraction circuit 19 is the MTF correction calculation circuit 12
The smoothed pixel level of interest input from the smoothing circuit 13 is subtracted from the MTF corrected pixel level of interest input from the smoothing circuit 13, and the subtraction result is output to the comparator A20. Specifically, from the MTF correction target pixel level data inputted from the MTF correction calculation circuit 12 as shown in FIG.
When the smoothed pixel level data of interest inputted from the smoothing circuit 13 as shown in FIG. 9 is subtracted, a subtraction result as shown in FIG. 9 is output.

Comparator A20 compares the subtraction result input from subtraction circuit 19 with a predetermined threshold value A,
The comparison result is output to the block area determination circuit 21. The threshold value A (reference value) is set to determine the halftone image area in the halftone image area. The subtraction circuit 19 and the comparator A20 have a function as a halftone dot area discriminating means for discriminating a halftone dot image area in a halftone image area.

The block area determination circuit 21 includes a comparator A20, a comparator B17, and a comparator C18.
Based on the respective comparison results inputted from the , the image area determination process of the pixel of interest, which will be described later, is executed, and the determination result is output to the selection circuit 23 . The timing delay circuit 22 is
Fixed threshold binarization circuit 14, dither processing circuit A15
Fixed binary image data and multivalued 2 based on smoothed matrix data input from the dither processing circuit B16 and dither processing circuit B16, respectively.
Valued image data and multivalued binary image data based on matrix data are output to the selection circuit 23 in accordance with the line delay and pixel delay timing in the block area determination circuit 21.

The selection circuit (selection means) 23 selects multivalued fixed binary image data input from the timing delay circuit 22 and smoothed matrix data based on the image area determination result input from the block area determination circuit 21. Binary image data and multi-value binary image data based on matrix data are selected and output to the next stage memory 9 as output binary image data.

Returning to FIG. 2 again, the memory 9 stores a predetermined amount of binarized image data input from the binarization calculation processing section 8, and transfers the accumulated binarized image data to the I/F at a predetermined timing.
It is output to the processing unit 10. The I/F processing unit 10 has a control function that matches the transfer procedure and connection form for transferring binarized image data to a connected host device (data processing device such as a computer, communication device, etc.) not shown in the figure. It outputs the binarized image data input from the memory 9 to the connected host device.

Although FIG. 2 mainly shows the flow of image data, it goes without saying that the scanner device 1 as a whole is further provided with a control section for controlling the entire device. Next, the effect will be explained. When an operator sets a document to be read by the scanner device 1 on the document table 3 or the ADF section 4, the document image is read line by line by the image reading section 6, and analog image data is output to the shading processing section 7, where shading is performed. The processing unit 7 converts the data into digital multilevel image data and outputs it to the binarization calculation processing unit 8 .

The binarization calculation processing unit 8 determines whether the digital multilevel image data inputted from the shading processing unit 7 is a character image area, a halftone image area, or a halftone image area. The region discrimination process and the image signal binarization process associated with the region discrimination are performed as follows. First, when digital multivalued image data is input to the binarization calculation processing unit 8, the matrix forming circuit 11 generates data as shown in FIGS. 3×3 or 3×5 two-dimensional matrix data is formed, and this matrix data is sent to the MTF correction calculation circuit 1.
2 and the smoothing circuit 13 perform MTF correction processing and smoothing processing. These matrix data, MTF correction matrix data, and smoothing matrix data are shown in Figure 10.
As shown in FIG. 6, it is compared whether the pixel level of interest in the MTF correction matrix data is greater than the threshold value B shown in FIG. The pixel is determined to be a character image in the character image area (step S2
), and based on this judgment result, the selection circuit 23 selects the fixed binary image data obtained by binarizing the pixel of interest in the MTF correction matrix data in the fixed threshold binarizing circuit 14 as the output binary image data. The data is then output to the next stage memory 9, and the process ends (step S3).

On the other hand, if the level of the pixel of interest in the MTF correction matrix data is not greater than the threshold value B in step S1, it is determined whether the level of the pixel of interest in the smoothing matrix data is smaller than the threshold value C shown in FIG. If it is smaller than the threshold value C, the pixel of interest is determined to be a white image in the character image area, the fixed binary image data is selected as the output binary image data, and the next step is The process is then output to the memory 9 of the stage (steps S2 and S3).

Further, if the target pixel level in the smoothing matrix data is not smaller than the threshold value C in step S4, the difference data between the MTF correction matrix data and the smoothing matrix data output from the subtraction circuit 19 is It is compared whether it is larger than a threshold value A as a point image area discrimination value (step S5), and if it is larger than the threshold value A, the block area judgment circuit 21 determines that the pixel of interest is a halftone image in a halftone image area. (Step S6), and based on this judgment result, the selection circuit 23 outputs and binarizes the multi-stage binarized image data obtained by binarizing the pixel of interest in the smoothed matrix data in the dither processing circuit A15. The image data is selected as image data and output to the next stage memory 9, and the process ends (step S7).

If it is not larger than the threshold value A in step S5, the block area determination circuit 21 determines that the pixel of interest is a halftone image that does not include a halftone image (step S8), and based on this determination result, the selection circuit 23 is a dither processing circuit B16 which selects multi-stage binary image data obtained by binarizing the pixel of interest in the matrix data as output binary image data and outputs it to the next stage memory 9 for processing. (Step S9).

Specifically, for example, when image data is divided into blocks as shown in FIG. 11, and one block is composed of 8×8 pixels, an image based on area determination data for each block is Area determination is performed and the image is divided into character image blocks, halftone image blocks, and halftone image blocks. Fixed binary image data, multi-stage binary image data for smoothing processing, and multi-stage binary image data for matrix data, which are output after timing adjustment by the timing delay circuit 22 based on the determined result, are selected by the selection circuit. In step 23, the image data is selected based on the area determination result and output as output binary image data to the next stage processing circuit.

Therefore, since the binarization processing calculation section 8 can be commonly used to perform binarization processing on character images, halftone images, and halftone dot images, image areas can be appropriately divided without increasing the circuit scale. can be determined and binarized, and the image quality of the read image can be improved at low cost. 12 to 18 are diagrams showing an embodiment of a scanner device to which the image device according to the second and third aspects of the invention is applied.

FIG. 12 is a block diagram of a schematic configuration of the scanner device 31. Components that are the same as the schematic configuration of the scanner device 1 shown in FIG. In FIG. 12, the binarization arithmetic processing circuit 32 includes a matrix forming circuit 41, an MTF as shown in FIG.
Correction calculation circuit 42, dither processing circuit 43, edge extraction circuit 44, surrounding pixel density comparison section 45, comparator A46
, comparator B47, OR circuit 48, AND circuit 49
, a selection circuit A50, and a selection circuit B51.

The matrix forming circuit (matrix forming means) 41 is composed of a line buffer and a latch that forms a two-dimensional space centered on the pixel of interest of input digital multivalued image data (multivalued pixel signal). , two-dimensional matrix data is formed that indicates the density level of the pixel of interest and the density levels of surrounding pixels on the front, rear, left, and right sides adjacent to the pixel of interest. For example, as shown in FIGS. x3 matrix data is formed and output to the MTF correction calculation circuit 42, dither processing circuit 43, edge extraction circuit 44, surrounding pixel density comparison section 45, comparator A46, and comparator B47.

MTF correction calculation circuit (correction binarization means) 4
2 performs filter calculation processing on the matrix data input from the matrix forming circuit 41 using a predetermined correction filter, that is, performs MTF correction processing on the blurred image, and then converts the MTF-corrected pixel data of interest to a predetermined fixed threshold value ( Binarization processing is performed by comparing with a fixed reference value),
It is output to the selection circuit B51 as fixed binary image data.

Dither processing circuit (multi-stage binarization means) 43
performs binarization processing by comparing the target pixel data of the matrix data inputted from the matrix forming circuit 41 with a threshold value (multi-stage reference value) set in a predetermined multi-stage,
It is output to the selection circuit A50 as multi-level binary image data. The edge extraction circuit (edge extraction means) 44 converts the matrix data inputted from the matrix formation circuit 41 into the form shown in FIG.
6 and 17, the edge component of the pixel data of interest is extracted, and the edge data is compared with a predetermined reference value and binarized to produce an edge binarized image. It is output as data to the AND circuit 49 and the selection circuit A50.

Surrounding pixel density comparison section (surrounding density comparison means)
45 compares the surrounding pixel level in the matrix data inputted from the matrix forming circuit 41 with a threshold value C set for predetermined density determination, and outputs the predetermined comparison result data to the AND circuit 49. For example, as shown in FIG. 18, the circuit configuration of the surrounding pixel density comparison unit 45 is such that when applied to the 3×3 matrix data shown in FIG. 15, surrounding pixel levels A, B, D,
Comparators 61 to 64 compare each E with a set threshold value C, and each comparison result data is output from an OR circuit 65.

Comparator A46 and comparator B4
7 is a threshold value A as shown in FIG. 19, in which the pixel level of interest in the matrix data inputted from the matrix forming circuit 41 is set as a reference value for determining pixel density.
, B, and output the comparison results to the OR circuit 48. Comparator A46 outputs predetermined comparison result data when the pixel level of interest is greater than set threshold value A, and comparator B47 outputs predetermined comparison result data when the pixel level of interest is smaller than set threshold value B. do. Setting threshold value A, B
(Text image area determination value) is set to determine whether the pixel of interest is a character image area or a halftone image area.

Comparator A46 and comparator B47
has a function as a character area discrimination means. The OR circuit 48 performs OR processing on the comparison result data input from the comparators 46 and 47 and outputs the result to the selection circuit B51. The AND circuit 49 performs AND processing on the edge binarized image data input from the edge extraction circuit 44 and the comparison result data input from the surrounding pixel density comparison section 45, and sends the selection circuit A50 to the selection circuit A50.
Output to.

The output from the OR circuit 48 indicates that the pixel of interest is a character image area, and the output from the AND circuit 49 indicates that the pixel of interest is an edge image area in a halftone image area. The selection circuit A50 selects the dither processing circuit 43 and the edge extraction circuit 44 based on the AND processing output of the edge binarized image data and the comparison result data inputted from the AND circuit 49, that is, whether it is a character image area or a halftone image area. Multivalued binary image data and edge 2 input from
The converted image data is selectively selected and outputted to the selection circuit B51.

The selection circuit B51 receives input from the MTF correction calculation circuit 42 and the selection circuit A50 based on the OR processing output of the comparison result data input from the OR circuit 48, that is, whether it is a halftone image area or an edge image area. The corrected binary image data, multi-value binary image data, or edge binary image data are selected and outputted to the memory 9 at the next stage as output binary image data.

The selection circuit A50 and the selection circuit B51 have a function as selection means. Note that although FIG. 12 mainly shows the flow of image data, the scanner device 1
Of course, the apparatus as a whole is further provided with a control section that controls the entire apparatus. Next, the effect will be explained.

When an operator sets a document to be read by the scanner device 31 on a document table (not shown) or an ADF section, the document image is read line by line by the image reading section 6 and analog image data is sent to the shading processing section 7. The data is outputted, converted into digital multilevel image data by the shading processing section 7, and outputted to the binarization calculation processing section 32.

The binarization calculation processing unit 32 determines whether the digital multivalued image data inputted from the shading processing unit 7 is a character image area, a halftone image area, or an edge image area. The image signal binarization process associated with the discrimination process and area discrimination is performed as follows. First, 2
When digital multilevel image data is input to the digitization calculation processing unit 32, the matrix forming circuit 41 generates a 3×5 image data as shown in FIGS. Alternatively, 3×3 two-dimensional matrix data is formed, and this matrix data is processed by the MTF correction calculation circuit 42, dither processing circuit 43, and edge extraction circuit 44 to perform MTF correction binarization processing, dither binarization processing, and edge extraction 2. As the value processing is performed, as shown in FIG. 20, the comparator A46 compares whether the pixel of interest in the matrix data is larger than the threshold value A shown in FIG. If the pixel of interest is larger, it is determined that the pixel of interest is a character image in the character image area, and the selection circuit B51 selects the MTF correction calculation circuit 4.
The fixed binary image data input from 2 is selected as the output binary image data and output to the next stage memory 9, and the process ends (step T2).

On the other hand, if the level of the pixel of interest in the matrix data is not greater than the threshold value A in step T1, the comparator B47 determines whether the level of the pixel of interest in the matrix data is smaller than the threshold value B shown in FIG. The comparison is made (step T3), and if it is smaller than the threshold value B, it is determined that the pixel of interest is a white image in the character image area, the fixed binary image data is selected as the output binary image data, and the next step is performed. The process is then output to the memory 9 (step T2).

If the pixel level of interest is not smaller than the threshold value B in step T3, the edge extraction circuit 44 checks whether the pixel of interest has been extracted as edge data (step T4). If it is not edge data, the pixel of interest is determined to be a halftone image, and the selection circuit A50 and selection circuit B51 select the multi-stage binary image data input from the dither processing circuit 43 as output binary image data. It is selected and output to the next stage memory 9, and the process ends (step T5).

Further, when the pixel of interest is edge data in step T4, the surrounding pixel density comparison unit 45 compares whether the surrounding pixel level of the matrix data is smaller than the set threshold value C for density determination, and 1 in
If at any time there is a pixel smaller than the threshold value C,
The pixel density below the threshold value C is taken as the original background density, and the pixel of interest is determined to be an edge image for the background density, and the edge binary image data is input from the edge extraction circuit 44 in the selection circuit A50 and the selection circuit B51. is selected as the output binary image data and output to the next stage memory 9, and the process ends (step T7). Therefore, the character image,
Since the binarization processing calculation unit 32 can be used in common to perform binarization processing on halftone images and edge images in the halftone images, image areas can be determined appropriately without increasing the circuit scale. Binarization processing can be performed, and the image quality of read images can be improved at low cost. Furthermore, by providing the edge extraction circuit 44, it is possible to prevent false detection of edges in character image areas and avoid excessive edge enhancement in halftone image areas, further improving the image quality of halftone images. can be done. Furthermore, by making it possible to arbitrarily set the set threshold values A, B, and C, it is also possible to obtain a read image desired by the operator.

Furthermore, by fixing the comparison output data of the surrounding pixel density comparison section 45 to, for example, the logic output "1", the edge data in the halftone image area can be output as is, It is also possible to separate the character image area and the halftone image area and output a high contrast read image with edge emphasis added.

[0050]

According to the invention as set forth in claim 1, matrix data is formed from input pixel signals, an image area is determined from the pixel level of interest in the matrix data, and when the input pixel signal is a character image area, A fixed binary image signal is selected and output as the output binary image signal, and when the input pixel signal is in a halftone image area, a multi-level binary image signal obtained by smoothing the matrix data is output and binarized. When the input pixel signal is in a halftone image area, a multi-level binary image signal based on matrix data is selected and output as the output binary image signal, so it is not expensive. Without using high-speed processing circuits, it is possible to appropriately and quickly identify the character image area, halftone image area, and halftone image area of a document image containing a mixture of binary images and halftone images. The processing device can be made inexpensive, and the pixel signals in the binary image area, halftone image area, and halftone image area can be appropriately binarized to prevent lines from becoming thinner or thicker. It is possible to improve the image quality.

In the invention according to claim 2, matrix data is formed from the input pixel signal, an image area is determined from the pixel level of interest in the matrix data, and when the input pixel signal is a character image area, the matrix data is determined based on the correction matrix data. A fixed binary pixel signal is selected and output as the output binary pixel signal, and when the input pixel signal is in a halftone image area, the level difference between the pixel of interest as an edge pixel and all surrounding pixels is a predetermined value. When it is determined that When it is determined that the input pixel signal is large, the edge binary image signal based on the edge data is selected and output as the output binary image signal. When it is identified that the level difference between the pixel of interest as an edge pixel and all surrounding pixels is less than a predetermined value, the edge binary image signal based on edge data is selected as the output binary image signal and output. Since the edge pixels in the halftone image area are emphasized, the text image area and halftone image of a document image containing a mixture of binary images and halftone images can be easily processed without using expensive high-speed processing circuits. The area and the edge image area can be appropriately and quickly identified, the image processing device can be made inexpensive, and
By appropriately performing binarization processing on pixel signals in the binary image area, halftone image area, and edge image area, lines can be prevented from becoming thinner or thicker, and image quality can be improved. Furthermore, a high contrast image can be obtained by emphasizing edge components in a halftone image area.

[Brief explanation of the drawing]

FIG. 1 is a perspective view of the external appearance of a scanner device to which an image processing device according to the invention according to claim 1 is applied.

FIG. 2 is a block diagram showing the configuration of a control system of a scanner device to which the image processing device according to the invention according to claim 1 is applied.

FIG. 3 is a block diagram showing the configuration of a binarization calculation processing section in FIG. 2;

FIG. 4 is a diagram showing matrix data formed by the matrix forming circuit of FIG. 3;

FIG. 5 is a diagram showing other matrix data formed by the matrix forming circuit of FIG. 3;

6 is a diagram showing the relationship between threshold values B and C compared by comparators B and C in FIG. 3 and a pixel of interest; FIG.

FIG. 7 is a diagram showing MTF correction data of a pixel of interest output from the MTF correction calculation circuit of FIG. 3;

FIG. 8 is a diagram showing smoothed data of a pixel of interest output from the smoothing circuit of FIG. 3;

FIG. 9 is a diagram showing subtraction data of a pixel of interest output from the subtraction circuit of FIG. 3;

FIG. 10 is a flowchart showing a program for image area determination processing and binarization processing that are processed by the block area determination circuit and selection circuit of FIG. 3;

FIG. 11 is a diagram showing a block configuration of image data processed in the image area determination process and binarization process of FIG. 10;

FIG. 12 is a block diagram showing the configuration of a control system of a scanner device to which the image processing device according to the second and third aspects of the invention is applied.

FIG. 13 is a block diagram showing the configuration of a binarization calculation processing section in FIG. 12;

FIG. 14 is a diagram showing matrix data formed by the matrix forming circuit of FIG. 13;

FIG. 15 is a diagram showing other matrix data formed by the matrix forming circuit of FIG. 13;

FIG. 16 is a diagram showing the configuration of a weighting filter used in edge extraction processing in the edge extraction circuit of FIG. 13;

FIG. 17 is a diagram showing the configuration of another weighting filter used in edge extraction processing in the edge extraction circuit of FIG. 13;

FIG. 18 is a diagram showing a circuit configuration of a surrounding pixel density comparison section in FIG. 13;

19 is a diagram showing the relationship between threshold values A and B compared by comparators A and B in FIG. 13 and a pixel of interest.

[Figure 20] Comparators A, B and selection circuit A in Figure 13
, B is a flowchart showing a program for image area discrimination processing and binarization processing that are processed in B.

[Explanation of symbols]

1, 31 Scanner device 2 Main body 3 Document table 4 ADF section 5 Paper ejection table 6 Image reading section 7 Shading processing section 8, 32 Binarization calculation processing section 9 Memory 10 I/F processing section 11, 41 Matrix forming circuit 12, 42
MTF correction calculation circuit 13 Smoothing circuit 14 Fixed threshold binarization circuit 15 Dither processing circuit A 16 Dither processing circuit B 17 Comparator B 18 Comparator C 19 Subtraction circuit 20 Comparator A 21 Block area determination circuit 22 Timing delay circuit 23 Selection circuit 43 Dither processing circuit 44 Edge extraction circuit 45 Surrounding pixel density comparison section 46 Comparator A 47 Comparator B 48 OR circuit 49 AND circuit 50 Selection circuit A 51 Selection circuit B

Claims (3)

[Claims] 1. An image processing device that binarizes a multi-value pixel signal input for each line based on a predetermined reference value for each pixel and outputs an output binary pixel signal. a matrix forming means for forming and outputting matrix data indicating the level of a pixel of interest and the level of adjacent pixels at the same position in the lines before and after the pixel of interest, and correcting the matrix data using a predetermined correction filter;
A correction means for outputting correction matrix data, a smoothing means for smoothing the matrix data and outputting smoothed matrix data, and a binarization process by comparing the pixel level of interest in the correction matrix data with a predetermined fixed reference value. A fixed binarization means outputs a fixed binarized pixel signal, and a binarization process is performed by comparing the pixel level of interest in the matrix data with a multi-step reference value that changes in multiple steps, and a multi-step binarized pixel signal is generated. A first multi-stage binarization means for outputting a signal performs binarization processing by comparing the pixel level of interest in the smoothed matrix data with a multi-stage reference value that changes in multiple stages, and generates a multi-stage binarized image signal. a second multi-stage binarization means for outputting; and an image area determining means for comparing the level of the pixel of interest in the correction matrix data with a predetermined area determination value to determine whether the pixel of interest is a character image area or a halftone image area. , a halftone area determining means for determining whether the pixel of interest is in a halftone image area by comparing the difference between the pixel level of interest in the correction matrix data and the pixel level of interest in the smooth matrix data with a predetermined reference value; and selecting a binarized image signal from one of the fixed binarization means, the first multi-stage binarization means, and the second multi-stage binarization means based on the discrimination result of the halftone area discrimination means. a selection means for outputting the fixed binary image signal as an output binary image signal, and when the input pixel signal is in a character image area, the selection means outputs the fixed binary image signal output from the fixed binary conversion means as the output binary image signal. When the input pixel signal is in a halftone image area, the multi-stage binarized image signal output from the first multi-stage binarized means is selected as the output binarized image signal. When the input pixel signal is in a halftone image area, the second multi-stage binarization means outputs a multi-stage 2
An image processing device that selects and outputs a digitized image signal as an output binary image signal. 2. An image processing device that binarizes a multi-value pixel signal input for each line based on a predetermined reference value for each pixel and outputs an output binary pixel signal. matrix forming means for forming and outputting matrix data indicating the level of a pixel of interest and the level of adjacent pixel signals at the same position in the lines before and after the pixel of interest;
Correction processing 2: correcting the matrix data using a predetermined correction filter to correct the pixel level of interest, comparing the pixel level of interest with a predetermined fixed reference value, performing binarization processing, and outputting a fixed binary pixel signal. a multi-step binarization means for performing binarization processing by comparing a pixel level of interest in the matrix data with a multi-step reference value that changes in multi-steps, and outputting a multi-step binarized image signal; Edges that weight the data using a predetermined weighting filter, extract the edge pixel level of the pixel of interest, compare the edge pixel level with a predetermined reference value, perform binarization processing, and output an edge binarized image signal. When an edge pixel is extracted by the extraction means, the character area determination means for comparing the level of the pixel of interest in the matrix data with a predetermined character image area determination value and determining whether the pixel of interest is in a character image area, and the edge extraction means, Surrounding density comparison means that compares each surrounding pixel of matrix data from which the edge pixel is extracted with a predetermined density determination reference value, and identifies a level difference between the edge pixel and each surrounding pixel serving as a background based on the comparison result. When the pixel of interest is a character image area, the fixed binarized pixel signal of the correction binarization means is selected and outputted as an output binarized image signal, and also based on the identification result of the surrounding density comparison means. a selection means for selecting one of the binary image signals from the multi-stage binarization means and the edge extraction means and outputting the selected binary image signal as an output binary image signal, and when the input pixel signal is in a character image area, The selection means selects and outputs the fixed binary pixel signal output from the correction binarization means as the output binary pixel signal, and when the input pixel signal is in a halftone image area, the surrounding density comparison means selects and outputs the fixed binary pixel signal output from the correction binarization means. When it is identified that the level difference between the pixel of interest and all surrounding pixels is less than a predetermined value, the selection means outputs a multi-stage binary image signal output from the multi-stage binarization means as a binary image signal. When the surrounding density comparison means identifies that at least one of the pixel of interest and the surrounding pixels as an edge pixel is larger than a predetermined value, the selection means selects and outputs the edge binarized image output from the edge extraction means. An image processing device that selects and outputs a signal as an output binary image signal. 3. In the invention according to claim 2, when the input pixel signal is in a halftone image area, the surrounding density comparison means determines that the level difference between the pixel of interest as an edge pixel and all surrounding pixels is a predetermined value. When it is identified that: An image processing device characterized by: