JPH04344947A - Program controller - Google Patents

Abstract

PURPOSE:To make the supplement of routine used exclusively for debugging unnecessary, and simultaneously to stop a program impartially at any timing of the execution of the program by checking whether a register designated arbitrarily reaches an expected value or not and stopping the program when it reaches the expected value. CONSTITUTION:A selection circuit 4 selects a bus output instruction register 3 and an instruction for outputting the contents of the optional register being used in a program device is supplied to an execution control part 5. Bus output data is supplied to a data coincidence detection circuit 8 and is compared with the data of a reference data register 7. Besides, an address coincidence circuit 11 compares an instruction address with the data of a reference address register 10 and only in the case that this data coincides, and in addition, the bus output coincides with the data of the reference data register 7, logic '1' is outputted to a signal line 120. The logic '1' signal is supplied to the execution control part 5 as a program stop signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program control device, and more particularly to a program control device having a debug function.

0002

2. Description of the Related Art Generally, in a program control device, in order to facilitate debugging of a program, execution of a program can be temporarily stopped at a predetermined address in a control storage unit where the program is stored. It has functions.

That is, the program control device is equipped with a comparison address register that stores address data for comparison with a control storage address (address data) supplied to the control storage section, and the contents of this comparison address register and the contents of the comparison address register are updated each time a program is executed. It has a function of comparing the control memory address supplied to the control memory unit and stopping the execution of the program if a match is detected between the two. When debugging, a control storage address in which an instruction to temporarily stop program execution is stored is input from, for example, a console, stored in a comparison address register, and then program execution is started. When the program stops at the specified instruction address (control memory address) using the above function, by checking the contents of various registers and other internal states in this state, the processing by the program is performed as desired. Check whether it is working. Once this is done, the next address to stop is specified again if necessary, and the program is restarted from the current stopped address (or any other address).

0004

[Problem to be Solved by the Invention] In the program control device described above, when debugging an arbitrary routine under the condition that a certain register has a certain value at the time of a certain instruction address, it is necessary to It is possible to stop at a specific routine address if you know what will happen, but
In general, programs cannot be predicted because they perform complex operations depending on the order of software instructions or external factors (interrupts from input/output devices, etc.), and in reality, programs cannot be stopped under such conditions.

To solve this problem, add a debugging routine that branches to a unique address (or executes an instruction that stops the program) when a register in a specific routine reaches a certain value. is possible. However, this is not done equally at all timings of program execution, and it is necessary to add a dedicated debugging routine each time where it is considered to be the minimum necessary.

SUMMARY OF THE INVENTION An object of the present invention is to provide a program control device that does not require the addition of a debugging routine and can equally stop a program at all timings of program execution.

[0007]

[Means for Solving the Problems] The program control device of the present invention includes an instruction register for storing a first instruction of a program read from a control storage means for storing the program, and an internal register for storing data to be compared. a bus output instruction register that stores a second instruction for outputting to the bus; a comparison data register that stores data for comparison with data on the internal bus; and a bus output instruction register that stores data for comparison with data on the internal bus; data comparing means for comparing the above data with the above data; and selecting means for selecting either the first instruction or the second instruction from the instruction register and the bus output instruction register and supplying the selected one to the instruction execution means. , a comparison address register for storing address data for comparison with the control storage address data supplied from the instruction execution means in the control storage means; and a comparison address register for storing the control storage address data and the address data from the comparison address register. The address comparison means to be compared and the second instruction stored in the bus output instruction register are supplied to the instruction execution means, the data comparison means detects a match with the data, and the address comparison means and control means for stopping instruction execution in the instruction execution means when a match between address data and the address data is detected.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing one embodiment of the present invention, a program control device includes a control memory 1, an instruction register 2,
, bus output instruction register 3, selection circuit 4, execution control unit 5
, a flip-flop (hereinafter abbreviated as F/F) 6, a comparison data register 7, a data coincidence detection circuit 8, an AND gate 9, a comparison address register 10, an address coincidence detection circuit 11, and an AND gate 12.

In this program control device, program instructions stored in the control storage unit 1 are stored in the execution control unit 5.
The command is read out to the command register 2 according to the command address generated by the command address and supplied through the signal line 50, selected by the selection circuit 4, and supplied to the execution control section 5 for execution. In this case, the output of the F/F 6 is logic "0", and the selection circuit 4 selects the instruction register 2. The F/F 6 has a function of inverting its value every time an instruction is executed, and becomes logic "1" after executing the instruction in the instruction register 2. As a result, the selection circuit 4 selects the bus output instruction register 3, and executes an instruction to output the contents of any register used in the program control device to the internal bus, although other than the instruction register is not shown. The signal is supplied to the control unit 5. The bus output data is supplied to the data match detection circuit 8 via the signal line 80 and compared with the data in the comparison data register 7. On the other hand, the contents of the instruction register 2 are held when the output of the F/F 6 is logic "1", and the instruction from the control storage unit 1 is stored only when the output is logic "0".

The above operation will be explained with reference to the timing chart shown in FIG. The clock in FIG. 2 is a clock for execution processing used within the program control device, and in the case of this figure, drives the operation switching of the F/F 6. When the output of the F/F 6 is logic "0" and the instruction A is stored in the instruction register 2, the instruction A is supplied to the execution control unit 5 and executed. As a result, the next instruction B to be executed is read from the control storage section 1 and stored in the instruction register 2. Also, at the same time, F/F6
By inverting the output to logic "1", the bus output instruction Z, which is the instruction stored in the bus output instruction register 3, is then supplied to the execution control unit 5 and executed. Thereafter, by repeating the same operation, the normal program A → B → C execution will be changed to A → Z → B → Z → C with a bus output instruction Z inserted between each instruction. Execution is realized. However, the bus output command Z only outputs an arbitrary register to the bus and does not change any hardware state.

During the above operation, the data coincidence detection circuit 8 compares the bus output with the data output of the comparison data register 7, and since the AND gate 9 performs a logical product with the output of the F/F 6, the signal Line 90 has a bus output command Z
A logic "1" is output only when the bus output from the comparison data register 7 matches the data output from the comparison data register 7.

Further, the address match detection circuit 11 compares the instruction address supplied via the signal line 50 with the data in the comparison address register 10, and furthermore, the AND gate 12 performs a logical product with the logic signal on the signal line 90. Therefore, a logic "1" is output to the signal line 120 only when the bus output by the bus output instruction Z and the comparison data register 7 match, and the instruction address and the data of the comparison address register 10 match. . This logic "1" signal is supplied to the execution control section 5 as a program stop signal.

Note that the bus output command register 3, comparison data register 7, and comparison address register 10 are supplied in advance with an instruction to instruct bus output of the register to be compared, expected data, and expected address from a console (not shown). Stored.

[0015]

[Effects of the Invention] As explained above, according to the present invention, during the execution of each instruction of a program, it is determined as a hardware operation whether a register arbitrarily specified by an arbitrarily specified instruction address has reached the expected value. By checking this and stopping the program when the expected value is reached, there is no need to add a dedicated debugging routine, and the program can be stopped equally at all timings of program execution. As a result, debugging becomes more efficient.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart showing a part of the operation in the program control device of this embodiment.

[Explanation of symbols]

1 Control storage unit 2 Instruction register 3 Bus output instruction register 4 Selection circuit 5 Execution control unit 6 Flip-flop (F/F) 7 Comparison data register 8 Data match detection circuit 9 AND gate 10 Comparison address register 11 Address match detection circuit 12 AND Gate

Claims (1)

[Claims] 1. An instruction register for storing a first instruction of the program read from a control storage means for storing the program, and a second instruction for outputting data to be compared to an internal bus. a bus output command register for comparing data on the internal bus, a comparison data register for storing data to be compared with data on the internal bus, and data comparison means for comparing data from the comparison data register with data on the internal bus; selecting means for selecting either the first instruction or the second instruction from the instruction register and the bus output instruction register and supplying the selected instruction to the instruction execution means; and supplying the instruction execution means to the control storage means. a comparison address register for storing address data to be compared with the control storage address data to be compared; address comparison means for comparing the control storage address data and the address data from the comparison address register; and the bus output instruction register. when the second instruction stored in the second instruction is supplied to the instruction execution means, the data comparison means detects a data match, and the address comparison means detects a match between the control storage address data and the address data; A program control device comprising: control means for stopping instruction execution in the instruction execution means.