JPH0434601Y2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to a circuit for detecting a pilot signal used in AM stereo broadcasting.

Prior art and problems Currently, in the United States, Magnavox, Kahn,
By mixed use of four types of Motorola and Harris methods
AM stereo broadcasting has been commercialized, and in order to identify which system it is, 5
Hz, 15Hz, 25Hz and 55Hz pilot signals are used.

Since the conventional pilot signal detection circuit is configured to directly supply the detection result to a subsequent tuning switching circuit, etc., there has been a problem in that it is sensitive to spurious signals such as noise and is likely to output erroneous detection results for a short period of time.

Purpose of the Invention The present invention is intended to improve the above-mentioned conventional drawbacks, and its purpose is to provide a pilot signal detection circuit that is less sensitive to spurious signals such as noise.

Structure of the invention The present invention that achieves the above object includes a pilot signal detection circuit that detects a plurality of types of pilot signals and outputs a detection logic value indicating the detection result of each pilot signal to a corresponding output terminal; The output of each latch circuit consists of a delay circuit that delays the detection logic value by a predetermined period of time, and a plurality of latch circuits that use the logic output of the delay circuit to latch the detected logic value and use the latch output to reset other latch circuits. is the detection output of each pilot signal.

Hereinafter, the present invention will be explained in further detail with reference to Examples.

Embodiment of the invention Figure 1 is a block diagram of an embodiment of the invention.
FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG.

In Fig. 1, 1 is a reception input terminal, 2 is a conventional pilot signal detection circuit, 3 and 4 are transistors, 5 and 6 are latch circuits, 7 and 8 are AND gates, 9 is a delay circuit, and 10 is a pulse generation circuit. ,1
1 and 12 are transistors, 13 is an inverter, 1
4 and 15 are output terminals.

The configuration of FIG. 1 exemplifies the case where two types of pilot signals are detected to simplify the explanation.
A reception signal including a pilot signal is supplied to a conventional pilot signal detection circuit 2 from a reception input terminal 1 connected to a reception circuit (not shown). This pilot signal detection circuit 2 may be a conventional type in which a level comparison circuit is placed after a resonant circuit, or it may be an improved type using a frequency/voltage conversion circuit according to the application filed by the present applicant. In any case, the pilot signal detection circuit 2 outputs detection outputs a and b which become low when the pilot signals A and B are detected at the output terminals 2-A and 2-B, respectively.

Assume that the pilot signal B is detected and the output b is low, as shown in FIG. In this case, transistor 4 becomes conductive and the signal
b' becomes high, and the latch circuit 6 that latches this high signal outputs a high signal from its output terminal C to the output terminal 15, thereby informing other circuits such as the tuning switching circuit that the pilot signal B is being received. indicate. The high output of the latch circuit 6 is supplied to the reset terminal D of the other latch circuit 5, and the latch circuit 5 thus reset outputs a low signal from its output terminal C to the output terminal 14, and the pilot signal A is Indicates to other circuits that it is not being received.

In this state, due to the influence of noise etc., the outputs a and b are limited for a short period from time t1 to t2.
Assume that the logical state of is inverted. The signal a' that rises accordingly is supplied to the delay circuit 9, passes through a diode, and is supplied to a differentiating circuit consisting of a capacitor and a resistor. As a result, the signal c supplied to the base of the transistor 11 in the figure rises rapidly and then gradually falls, and during the period when this signal c exceeds a predetermined threshold, the transistor 11
The output signal d of 1 falls to low.

The rising edge of this signal d passes through a diode and a differentiating circuit and becomes the base signal e of the transistor 12 in the next stage. This spike-like base signal e causes transistor 12 to conduct for a short period of time, and its output signal becomes low for a short period of time. This low state is inverted by the inverter 13, becomes a high signal, and is supplied to one input terminal of the AND gate 7. However, during the predetermined delay time τ from when the outputs a and b are inverted until the signal f falls, the signal a' supplied to the other input terminal of the AND gate 7 has already fallen to low. Therefore, the output of AND gate 7 remains low. As a result,
No enable signal (high) is input to the enable terminal B of the latch circuit 5, and the signal supplied to the input terminal A of the latch circuit 5 is not latched. In this way, even if the outputs a and b of the pilot signal detection circuit fluctuate for a short period of time due to the influence of noise, latches 5 and 6
The state of output terminal C of is not changed.

Thereafter, at time t3, when the outputs a and b of the pilot signal detection circuit are inverted, the signal f falls to low level with a delay of a predetermined time τ from the inversion of the outputs a and b based on exactly the same operation as described above. The inverted high signal is supplied to one input terminal of the AND gate 7, while the signal supplied to the other input terminal
Since a' also remains high, the output of AND gate 7 goes high and latch circuit 5 is enabled. As a result, the high signal a' is latched in the latch circuit 5, and the state of its output terminal C is inverted from low to high. This high signal is supplied to the output terminal 14 to indicate to other circuits such as the tuning switching circuit that the pilot signal A has been detected, and is also supplied to the reset terminal D of the other latch circuit 6 to reset the output of this latch circuit. Drops the state of terminal C from high to low. This low signal is applied to output terminal 15 to indicate to other circuits that pilot signal B is no longer being received.

In this way, the detection results at the output terminals 14 and 15 are changed only when the output of the pilot signal detection circuit 2 is inverted for a longer period than the predetermined delay time τ.

Although we have illustrated the case where there are two types of pilot signals,
The circuit shown in FIG. 1 can be easily expanded even if there are three or four types.

In the above example, a configuration using AND gates 7 and 8 was illustrated, but it is also possible to remove these AND gates and supply the output of the inverter 13 directly to the enable terminals B of the latch circuits 5 and 6. I can do it.

Effects of the Invention Since the present invention is configured as described above, it has the advantage of being able to effectively avoid false detections due to spurious signals such as noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention.
FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG. 1... Reception input terminal, 2... Conventional pilot signal detection circuit, 3, 4... Transistor, 5, 6
...Latch circuit, 7, 8...And gate, 9...
...Delay circuit, 10...Pulse generation circuit, 11,1
2...Transistor, 13...Inverter, 1
4, 15...Output terminal.

Claims (1)

[Claims for Utility Model Registration] A pilot signal detection circuit that detects a plurality of types of pilot signals and outputs a detection logic value indicating the detection result of each pilot signal to a corresponding output signal terminal; It consists of a delay circuit that causes a delay, and a plurality of latch circuits that latch the detected logic value by the logic output of the delay circuit and reset other latch circuits by the latch output, and the output of each of the latch circuits is connected to each pilot. Pilot signal identification circuit for signal detection output.