JPH0434656A - Initializing system for scan flip flop - Google Patents

Abstract

PURPOSE:To rapidly execute the initializing processing of a scan flip flop(FF) by initializing respective gates of a logical circuit to be initialized and the status value of the scan FF by logical simulation without executing reset simulation. CONSTITUTION:Respective gates of a logical circuit to be initialized and the status value of the scan FF in its initial state are registered in a reset value table 12, and at the time of initializing, respective gates of the circuit to be initialized and the initial value of the FF in corresponding gate and scan FF areas in a simulation table 11 to initialize the objective logical circuit. Thus, the gates of the objective logical circuit and the status value of the FF are initialized by logical simulation. Thus, the initializing processing time of each scan FF can be shortened.

Description

[Detailed Description of the Invention] [Summary] Regarding the scan flip-flop initialization method that initializes the state values of each gate and scan flip-flop of a target logic circuit in logic simulation, each gate and scan flip-flop in a simulation table is Hiscan・
The purpose is to speed up the initialization process of the state values of flip-flops, and it is equipped with a simulation table that stores the state values of each gate and scan flip-flop of the target logic circuit. In a scan flip-flop initialization method that initializes the state values of flip-flops using logic simulation, a reset value table is provided to register the state values of each gate of the target logic circuit and the scan flip-flops in their initial states. At the time of initialization, each initial value registered in the reset value table is written to each corresponding gate and scan flip-flop area in the simulation table.

[Industrial application field]

In a logic simulation in which a target logic circuit is simulated on a computer, the state values of each gate and scan flip-flop (flip-flop with a scan function, hereinafter referred to as scan FF) of the target logic circuit are calculated in the logic simulation. This invention relates to an initialization method for a scan flip-flop that is initialized by .

[Conventional technology]

BACKGROUND OF THE INVENTION As logic circuits in large-scale computers have become larger and more highly integrated in recent years, verification of the functionality and reliability of logic circuits has become increasingly important.

Verification of logic circuits is performed by logic simulation, which simulates the target logic circuit on a computer, but as logic circuits become larger and more integrated, the number of test patterns for logic circuits also increases. There is a growing demand for faster processing time for pattern creation or pattern verification. Among these, ■ Every time test pattern creation is completed, a reset simulation is performed to logically simulate the initial state of the logic circuit, but as the number of test patterns increases, this reset simulation processing The time required has become an issue.

The flip-flops that make up the logic circuit are configured to have a scan function to facilitate verification. The operations of this flip-flop with scan function, that is, scan FF, can be roughly divided into four types: clock operation, reset operation, scan-in operation, and scan-out operation.

In clock operation, input data is sampled when the clock is turned on, and when the clock is closed, the sampled data is held.

In the reset operation, a scan address is distributed to all flip-flops in the target circuit, and all flip-flops are asynchronously set/reset at the same time, thereby initializing their contents. This reset operation is
This is a necessary pre-operation before the scan-in operation.

In the scan-in operation, an operation is performed in which the contents of any one flip-flop selected by the scan address are set to a value opposite to that in the reset operation.

In the scan-out operation, the contents of any one flip-flop selected by the scan address are read out via a dedicated scan-out line.

Next, a conventional scan FF reset simulation method will be described with reference to FIGS. 3 to 5. FIG. 3 is an explanatory diagram of the configuration of an example of a logic circuit to be simulated and a simulation table;
FIG. 4 is an explanatory diagram of the detailed configuration of one example of scan FF, and FIG.
This is a chart.

In FIG. 3(a), 21 to 24 are logic elements constituting a logic circuit, and 31 to 35 are scan FFs.

Each of the scan FFs 31 to 35 has a detailed configuration as shown in FIG. 4, but only data input/output gates are shown as gates in FIG. 3(a).

CLK is a terminal into which a clock is input, PINI is a data input terminal of the scan FF 34, PIN2 is a data input terminal of the scan FF 35, and PIN3 is an output terminal of the logic element 22. These input/output terminals are the input gates of scan FF34, 35 and logic element 2.
Connect to each exit gate of 2.

In this configuration, when performing a functional test of each logic element 21 to 240, data for creating a predetermined test pattern that is different from its initial value is scanned in (SCAN-IN), that is, written to the scan FFs 31 to 35. .

Next, input the clock CLOCK once from the CLK terminal to input the value of each scan FF of the previous stage to each logic element 21 to 24 to perform calculation, and then input the value of each scan FF of the previous stage to each logic element 21-24.
A test pattern is created by scanning out (SCAN-OUT), that is, reading out the contents of 5.

By verifying this created test pattern, the function of each logic element can be verified.

For example, when performing a functional test on the logic element 210, data for creating a predetermined test pattern is scanned into the scan FFs 31 and 32, and then the clock CLOCK is input once from the CLK terminal.

As a result, the values scanned into the scan FFs 31 and 32 are added to the input gate of the logic element 210, and the calculation result of the logic element 21 is input to the scan FF 33.

Next, by scanning out the contents of the scan FF 35, a test pattern for functional testing of the logic element 21 is created. By verifying this created test pattern, the functionality of the logic element 210 can be verified.

When creating the next test pattern, each scan F
Set the contents of F31 to F35 to the predetermined initial state value (initial value)
need to be reset.

When resetting (initializing) each scan FF, initialize the contents by distributing the scan address to all scan FFs 31 to 35 in the target logic circuit and setting/resetting all scan FFs simultaneously asynchronously. The action is performed.

The above describes the scan-in, scan-out, and reset operations of the logic circuit to be simulated. When performing a logic simulation of this target logic circuit on a computer, the logic circuit shown in Fig. 3(b) A logic simulation is performed using the simulation table 40.

The simulation table 40 includes areas 41□ to 41n corresponding to each gate and scan FF of the target logic circuit.
Each area stores various types of logic information including corresponding gate and scan FF state values, and generally there are a plurality of areas.

Also, each area 41. Status value area 421-42 within ~41n
Each corresponding gate and scan FF state value is stored in n. Other portions of the areas 411 to 41n store information representing the target logic circuit, including information regarding the connection relationships of each gate and scan FF.

When performing logic simulation of the target logic circuit on a computer, the state values of each gate and scan FF during each clock operation, scan-in operation, scan-out operation, and reset operation of the target logic circuit are recorded in each area of the simulation table 40. This is performed by sequentially writing to 41+ to 42n.

Next, the detailed configuration and operation of the scan FF will be described with reference to FIGS. 4 and 5. Note that the following explanation is about the configuration and operation of the scan FF 31, but the explanation is also common to other scan FFs.

In FIG. 4, 311 to 316 are NOA circuits.

However, the NOA circuit 311 generates a positive logic output and a negative logic output (indicated by small white circles), and the NOA circuit 316 generates two negative logic outputs.

A clock signal (CLOCK) is input to the NOA circuit 311 . The NOA circuit 312 has data (DATA).
and the positive logic output of the NOA circuit 311 are input.

The negative logic output of the NOA circuit 311 , the output of the NOA circuit 315 , and the output of the NOA circuit 316 are input to the NOA circuit 313 .

On the other hand, the NOA circuit 314 has a scan address of 5A.
DR and the output of the NOA circuit 316 are input, and from the output gate, the scan F when the clock CLOCK is input.
A hold state signal (LSTA) that holds the state value of F
TE) is output.

A scan address 5ADR and a scan-in signal (SIN) are input to the NOA circuit 315. A reset signal (RESET) and the outputs of the NOA circuits 312 and 313 are input to the NOA circuit 316, and a state signal (STATE) representing the state of the flip-flop is output from its two output gates. One output is
It is input to the NOA circuit 314.

Next, the clock operation, reset operation, and scan-in operation of the logic circuit of FIG. 4 will be explained with reference to the operation timing chart of FIG. 5.

(1) Clock operation During clock operation, normal flip-flop operation is performed. During clock operation, as shown in FIGS. 5(b) and 5(b), the reset signal RESET is at a negative level and the scan-in signal SIN is at a positive level.

Therefore, when the negative level clock CLOCK shown in FIG. 5(a) is input, the input data DATA
is sampled by NOA circuits 311 and 312,
The NOA circuit 316 outputs sampled data (status signal 5TATE) as shown in FIG. 5(f).

Next, when the clock CLOCK closes, the NOA circuit 3
13 and 316 hold the data of the scan FF during sampling, and a hold state signal LSTATE is output as shown in FIG. 5(6).

(2) Reset operation During the reset operation, the clock signal CLOCK and scan-in signal SIN are at positive levels as shown in FIGS. 5(a) and 5(d). In addition, scan address signal 5
ADR is also at a negative level.

In this state, when the negative level reset signal RESET is input to the NOA circuit 316 as shown in FIG. 5(a), the state signal 5TA output from the NOA circuit 316
TE changes from a positive level to a negative level as shown in FIG. 5(f).

On the other hand, since all inputs to the NOA circuit 314 are at negative levels, the hold state signal LSTATE outputted therefrom is at a positive level as shown in FIG. 5(e).

(3) Scan-in operation During the scan-in operation, the clock signal CLOCK is at a positive level as shown in FIG. 5(a).

On the other hand, the reset signal RESET and scan address signal S^OR are both at negative level.

In this state, when scan-in No. 1 SIN at a negative level is input to NOA[i, 1315, as shown in FIG. 5(d), the output of the NOA circuit 315 becomes a positive level.

As a result, all the inputs to the NOA circuit 316 become negative levels, so that the state signal 5TATE outputted therefrom changes from a negative level to a positive level as shown in FIG. On the other hand, the NOA circuit 314 receives the positive level state signal 5TATE from the NOA circuit 316, and the output hold state signal LSTATE changes from a positive level to a negative level as shown in FIG. 5(e).

In this way, by the scan-in operation, the state signal 5TA
TE and the hold state signal LSTATE are changed to values opposite to their reset state values (initial values). Therefore, by comparing the state value of the created letter test pattern with the initial value of the corresponding scan FF, it is possible to verify whether the logic element is functioning normally or not.

When performing a logic simulation on a computer of a logic circuit using the scan FF described above, as described above, each gate and gate during each clock operation, scan-in operation, scan-out operation, and reset operation of the target logic The state values of the scan FFs are sequentially written into each of the 9M areas 411 to 42n of the simulation table 40.

For example, in the case of reset simulation, after distributing scan addresses to all scan FFs on the target logic circuit and causing all scan FFs to perform a reset operation, the reset value (initial value) of each scan FF is It is written to table 4o.

[Problem to be solved by the invention]

In the conventional simulation method, which initializes the state values of conventional scan FFs using logic simulation, the scan address is distributed to all scan FFs on the target logic circuit, and then reset to all scan FFs. After performing the operation, reset the reset value of each scan FF (
(initial value) was written into the simulation table 40.

In this way, the process of distributing scan addresses to all scan FFs on the target circuit takes time, and it is necessary to operate all the logic elements, so a reset to initialize the scan FFs in logic simulation is necessary. - There was an inconvenience that simulation processing took time and the overall logical simulation processing speed decreased.

Reset simulation is performed for each test pattern, so as the number of test patterns rapidly increases as logic circuits become larger and more highly integrated, the reset simulation processing time also increases This is extremely inconvenient because it increases in proportion to the number of .

The present invention provides an improved scan function that speeds up the initialization process of scan FFs by initializing the state values of each gate and scan FF of a target logic circuit in a logic simulation without performing a reset simulation. The purpose is to provide an FF initialization method.

[Means to solve the problem]

The means adopted by the present invention to solve the above-mentioned problems are as follows:
This will be explained with reference to the principle diagram shown in FIG.

In FIG. 1, reference numerals 11 (0)) and (C) in FIG. 1 are simulation tables in which state values of gates and scan flip-flops of the target logic circuit are stored.

The simulation table 11 has a similar configuration to the simulation table 40 shown in FIG. teeth,
Various types of logic information including state values of corresponding gates and scan FFs are stored, and generally a plurality of logic information exists.

In addition, each area 111. A state value area 112 within ~111n,
~112n stores the corresponding gate and scan FF state values. The other portions of the areas 111° to 1lln store information representing the target logic circuit, including information regarding the connection relationships of each gate and scan FF.

The state values of each of the state value regions 1121 to 112n shown in FIG.
The value of n indicates the initial value after each corresponding gate and scan FF are reset.

Reference numeral 12 in FIG. 5A is a reset value table, which includes reset value areas 1211 to 121n corresponding to each gate and scan FF of the target logic circuit, and each reset value area includes each corresponding gate and scan FF. A state value at the time of resetting the FF, that is, an initial value is registered. The present invention is implemented using the Seratoi direct table 11 and simulation table 12 shown in FIG. 1, and is constructed as follows. In other words, a simulation table (
11), in which the scan flip-flop initialization method initializes the state values of the gates and scan flip-flops of the target logic circuit on logic simulation, (a) a reset value table (12) is provided; Register the state values of each gate and scan flip-flop in the initial state of the logic circuit, and (b) at the time of initialization, register the state values of each gate and scan flip-flop of the target logic circuit registered in the reset value table (11). The simulation table (11) is configured to initialize by writing an initial value to each corresponding gate and scan flip-flop area in the simulation table (11).

[For production]

Although there are an extremely large number of test patterns for testing whether a target logic circuit operates in a predetermined manner, the initial state values at the time of creating each test pattern are all common.

Therefore, in the present invention, a reset value table 12 is provided,
The initial state values of each gate and scan FF of the target logic circuit are determined in advance and registered in the reset value table 12. As a result, the reset value area 121 t ~
121n, the initial values of each gate and scan FF of the target logic circuit are registered, as shown in FIG. 1(a). Since the initial value of each gate and scan FF takes the value O or 1 corresponding to its initial state, ・Reset value tM
The initial values of M 121, to 121n generally take the value of O or l as shown.

On the other hand, in each of the m* regions 112t to 112n of the simulation table 11, the state values of each scan FF and gate scanned in in the previous test pattern are stored as shown.

When the verification process of the previous test pattern is completed and the next test pattern is created, each scan FF is reset, so the simulation table 11
It is also necessary to update the contents of each state information value range 1121 to 112n to the initial value of the corresponding scan-in.

In the present invention, the initial values registered in the reset value areas 1211 to 121n of the reset value table 12 are
2. By writing to 112n, the simulation table 11 is initialized as shown in FIG. 1(C).

As a result, unlike the conventional reset simulation method, all scan FFs on the target logic circuit are scanned and
It is no longer necessary to distribute addresses and perform reset operations on all scan FFs, and simulation table 1
The contents of each state value area 1121 to 112n in 1 can be initialized easily and quickly.

As described above, in the present invention, the values in the initial state of each gate and scan FF of the target logic circuit are obtained in advance,
By writing the initial values into the simulation table 11, each gate and scan FF of the target logic circuit is initialized, so there is no need for a reset simulation operation like in the conventional method, and each scan FF is Initialization processing time can be significantly reduced.

In addition, by using the initial state value of each scan FF determined once, different test patterns can be commonly initialized. As the number increases, it is possible to increase the effect of shortening the initialization processing time compared to the conventional method in which initialization is performed by reset simulation.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is an explanatory diagram of the implementation system of the same embodiment. FIG. 3 is an explanatory diagram of the logic circuit to be simulated according to the same embodiment, and its configuration and operation contents are as described above.

(A) Configuration of implementation system In FIG. 2, a simulation table 11, each area 111 provided therein. ~ 111n, status value area 112 in each area, 112n and reset value table 12, each reset value area 121 provided therein
The contents of 1 to 121n are as explained in FIG.

Each state value region 112 shown in Φ) in the figure. Each state value of ~112n is the value before resetting each gate and scan FF, and each state value of each region 111, ~1lln shown in FIG.
The values indicate the initial values after the corresponding gates and scan FFs are reset, that is, the initial values.

A processor 13 performs logic simulation processing on the target logic circuit.

14 is a memory device in which a control program for controlling the logic simulation processing performed by the processor 13 is stored. Note that the simulation table 11 and the reset value table 11 may be provided in the memory device 14.

(B) Operation of the Embodiment An embodiment of the present invention will be described by taking as an example a case where the logic circuit shown in FIG. 3 is initialized on a logic simulation. Note that each process and operation described below is executed by the processor 13 according to a control program of the memory device 14 unless otherwise specified.

First, prior to the start of the logic simulation process, values in the initial state of each gate and scan FF of the target logic circuit are determined in advance and registered in the reset value table 12.

FIG. 2(a) illustrates a case where Oll and 0 are registered as initial values of the scan FFs 31, 32, and 33 in the reset value areas 12L, 121a, and 121 of the reset simulation 12. The initial values of other scan FFs and each gate are also registered in the corresponding reset value area in the same way (not shown).

On the other hand, in each state value area 1121 to 112n of the simulation table 11, the state values of each scan FF and gate scanned in in the previous test pattern are stored as shown.

In FIG. 2(b), areas 1112, 1114 and 111
, state value areas 112□, 112. A case is illustrated in which l, 0, and 1 are registered as the state values of the scan FFs 31, 32, and 112. Other scan F
The state values of F and each gate are similarly stored in the corresponding state value areas.

When the verification process of the previous test pattern is completed and the next test pattern is created, each gate and scan FF of the target logic circuit are initialized, so each state in the simulation table 11 is Range 112. ~11
The contents of 2n are updated to the initial values of the corresponding gates and FFs.

That is, reset value area 1 of the reset value table 12
21. The initial values registered in ~121n are transferred to the corresponding state value area 112 in the simulation table 11.
1 to 112n, the contents of each state value area 1121 to 112n in the simulation table 11 can be easily and quickly initialized, as shown in FIG. 1(C).

An embodiment of the present invention has been described above, taking as an example a logic simulation of the logic circuit shown in FIG. 3, but the present invention is not limited to this embodiment. Similarly, initialization can be performed on logic simulation.

〔effect〕

As explained above, according to the present invention, the following effects can be obtained.

(1) Obtain the initial state values of each gate and scan FF of the target logic circuit in advance, and perform the simulation.
By writing the initial values in Table 11, each gate and scan FF of the target logic circuit is initialized, so the cent simulation operation that is required in the conventional method is no longer necessary, and the initialization process of each scan FF is eliminated. The time can be significantly reduced.

(2) By using the initial state B (! of each scan FF obtained once), different test patterns can be commonly initialized. As the number of test patterns increases, the reset
Compared to the conventional method in which initialization is performed by simulation, it is possible to increase the effect of shortening the initialization processing time.

[Brief explanation of the drawing]

FIG. 1 is a diagram of the principle of the present invention, FIG. 2 is an explanatory diagram of the configuration of an implementation system of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the configuration of a logic circuit to be subjected to logic simulation and a simulation table, and FIG. The figure is an explanatory diagram of the configuration of the scan FF of the same logic circuit, and FIG. 5 is an operation timing chart of the same scan FF. In FIG. 1 and FIG. 2, 11...Simulation table, 1111-1
lln-...area, 112+ to 112n...state value area, 12...reset value table, 1211-1
21n...Reset value area. 13...processor,
14...Memory device. Figure 4: Configuration of scan FF in logic circuit

Claims (1)

[Claims] A simulation table (in which state values of each gate and scan flip-flop of the target logic circuit are stored)
11), in which the state values of the gates and scan flip-flops of the target logic circuit are initialized on logic simulation, (a) a reset value table (12) is provided, Register the state values of each gate and scan flip-flop in the initial state of the logic circuit, and (b) at the time of initialization, register the state values of each gate and scan flip-flop of the target logic circuit registered in the reset value table (11). An initialization method for a scan flip-flop, characterized in that initialization is performed by writing an initial value into each corresponding gate and scan flip-flop area in a simulation table (11).