JPH0434736U - - Google Patents
Info
- Publication number
- JPH0434736U JPH0434736U JP7638090U JP7638090U JPH0434736U JP H0434736 U JPH0434736 U JP H0434736U JP 7638090 U JP7638090 U JP 7638090U JP 7638090 U JP7638090 U JP 7638090U JP H0434736 U JPH0434736 U JP H0434736U
- Authority
- JP
- Japan
- Prior art keywords
- impurity region
- mos transistor
- semiconductor device
- vertical
- vertical mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000012535 impurity Substances 0.000 claims 5
- 239000004065 semiconductor Substances 0.000 claims 3
- 230000005611 electricity Effects 0.000 claims 1
- 239000000523 sample Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
第１図は本考案の一実施例のウエハ状態の平面
図、第２図はチエツク用チツプの断面図、第３図
はリーチスルー電圧とベース間距離との関係を示
す図、第４図は本考案の他の実施例のチエツク用
チツプの断面図、第５図は縦型ＭＯＳトランジス
タの断面図、第６図は縦型ＭＯＳトランジスタの
抵抗成分を示す図、第７図はオン抵抗とベース間
距離を示す図である。
１……Ｎ＋型基板、２……Ｎ型領域、３，３Ａ
……Ｐ型領域、４，４Ａ……Ｎ＋型領域、５……
ゲート電極、６……ゲート酸化膜、７……絶縁膜
、８……ソース電極、９……ドレイン電極。
FIG. 1 is a plan view of a wafer according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a check chip, FIG. 3 is a diagram showing the relationship between reach-through voltage and distance between bases, and FIG. 5 is a cross-sectional view of a vertical MOS transistor, FIG. 6 is a diagram showing the resistance component of the vertical MOS transistor, and FIG. 7 is a diagram showing the on-resistance and base FIG. 1...N + type substrate, 2...N type region, 3, 3A
...P type region, 4,4A...N + type region, 5...
Gate electrode, 6... Gate oxide film, 7... Insulating film, 8... Source electrode, 9... Drain electrode.
Claims (1)
スタチツプとともにチエツク用チツプを形成し、
このチエツク用チツプは縦型ＭＯＳトランジスタ
を構成する不純物領域と同時に形成した不純物領
域を有し、かつこの不純物領域には試験用プロー
ブを接触させて通電可能に構成したことを特徴と
する半導体装置。 ２ チエツク用チツプの不純物領域は、縦型ＭＯ
Ｓトランジスタのベース領域と同時に、またはソ
ース領域と同時に形成した不純物領域である実用
新案登録請求の範囲第１項記載の半導体装置。[Claims for Utility Model Registration] 1. Forming a check chip together with a large number of vertical MOS transistor chips on a semiconductor wafer,
A semiconductor device characterized in that this checking chip has an impurity region formed at the same time as an impurity region constituting a vertical MOS transistor, and is configured so that a test probe can be brought into contact with this impurity region to conduct electricity. 2 The impurity region of the check chip is a vertical MO
The semiconductor device according to claim 1, which is an impurity region formed simultaneously with a base region or a source region of an S transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990076380U JP2530722Y2 (en) | 1990-07-18 | 1990-07-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990076380U JP2530722Y2 (en) | 1990-07-18 | 1990-07-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0434736U true JPH0434736U (en) | 1992-03-23 |
| JP2530722Y2 JP2530722Y2 (en) | 1997-03-26 |
Family
ID=31617798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990076380U Expired - Lifetime JP2530722Y2 (en) | 1990-07-18 | 1990-07-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2530722Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107045995A (en) * | 2016-02-09 | 2017-08-15 | 富士电机株式会社 | The manufacture method of evaluation method and semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4998982A (en) * | 1972-12-29 | 1974-09-19 | ||
| JPS59194444A (en) * | 1983-04-19 | 1984-11-05 | Toshiba Corp | Monitoring semiconductor device and monitoring method |
-
1990
- 1990-07-18 JP JP1990076380U patent/JP2530722Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4998982A (en) * | 1972-12-29 | 1974-09-19 | ||
| JPS59194444A (en) * | 1983-04-19 | 1984-11-05 | Toshiba Corp | Monitoring semiconductor device and monitoring method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107045995A (en) * | 2016-02-09 | 2017-08-15 | 富士电机株式会社 | The manufacture method of evaluation method and semiconductor device |
| US10553505B2 (en) | 2016-02-09 | 2020-02-04 | Fuji Electric Co., Ltd. | Assessment method, and semiconductor device manufacturing method |
| CN107045995B (en) * | 2016-02-09 | 2023-02-17 | 富士电机株式会社 | Evaluation method and manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2530722Y2 (en) | 1997-03-26 |
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