JPH0434828B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to semiconductor integrated circuit technology and to technology that is particularly useful when applied to the formation of power supply wiring in semiconductor integrated circuit devices. This invention relates to a technique that is effective for forming power supply wiring to an output buffer in large-scale integrated circuits.

[Background Art] Conventionally, power wiring from a power pad 2 to an output buffer in an LSI is generally performed by a common power wiring 3 as shown in FIG. However, if the power supply wiring method described above is applied to a logic LSI having a large number of output buffers, such as a CRT controller, for example, as shown in _{FIG .} When the 1an outputs _A1 to An operate to change from high level to low level all at once as shown in Figure 3, a large transient current flows through the power supply wiring 3, and due to the impedance component of the power supply wiring 3, , the low level of the output B of the other output buffer 1b, which shares the power supply wiring 3 and operates in synchronization with the clock φ ₂ with different timing, momentarily rises and noise n is generated. As a result, there is a risk that the circuit receiving the output B of the output buffer 1b may malfunction or may erroneously latch data.

By the way, as a method to prevent malfunctions due to power supply noise between circuits that share a common power supply wiring, an invention has been proposed in which a separate power supply wiring is drawn out from the power supply pad for each circuit block to supply the power supply voltage. (For example, patent application 1983-38519)
issue).

However, these configurations are characterized by dividing the wiring depending on the magnitude of current consumption, and are not effective against output buffer noise.

[Object of the Invention] An object of the present invention is to provide a power supply wiring system that prevents the operation of one output buffer from causing noise in the output signal of another output buffer, thereby preventing malfunction of an LSI. Our goal is to provide the following.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] Representative inventions disclosed in this application will be summarized as follows.

In other words, all LSI output signals must not be captured by other LSIs at the same timing.
Also, if there is no noise when the output signal is latched, even if there is noise at other times, the output signal will be
Focusing on the fact that it does not cause malfunction of the LSI, the output signal of the output buffer at a certain timing is latched by dividing the power wiring and supplying the power supply voltage to each output buffer with different timing. This achieves the above object of preventing malfunction of the LSI by preventing noise from being generated due to changes in the output of the output buffer at different timings when the LSI is in use.

[Embodiment] FIG. 1 shows a basic configuration when the present invention is applied to wiring for supplying power supply voltage Vss to an output buffer of an LSI.

In this embodiment, a plurality of output buffers 1a ₁ , 1a ₂ , . . . 1 are operated in synchronization with the clock φ ₁ .
Separate power supply pads _2a and 2b are provided according to the output buffers _{1b1 to} 1bm, which are operated in synchronization with the clock φ2 having a timing different from the clock φ1, or not synchronized with the clock at all. A power supply voltage Vss, such as a ground potential, is supplied through separate power supply wirings 3a and 3b drawn out from the pads 2a and 2b.

According to the wiring method described above, for example, as shown in FIG. 4, among the output buffers 1a ₁ to 1an that are operated in synchronization with the clock φ ₁ , only the output An of 1an remains at a low level and does not change, while the other output buffers The outputs A1 to A(n- ₁ ) of _1a1 to _1a (n- ₁ ) all change from high level to low level at the same time,
Assume that a large transient current is passed through the power supply wiring 3a. Then, due to this transient current, the power supply voltage Vss
The potential rises and the output buffer is 1an.
Noise n appears in An'. Therefore, in the circuit receiving the outputs A ₁ to An of these output buffers 1a ₁ to 1an, the timing of the change (rising in the embodiment) of the clock φ ₁ is slightly delayed, and
The outputs _{A 1} -An are often latched at a timing shown by T ₂ when the outputs of the output buffers 1a ₁ -1an become stable. Therefore, even if the noise n' of the output An rises due to the influence of the output change of the output buffers 1a ₁ to 1a (n- ₁ ),
Since the noise n' occurs at a timing T that is different from the timing _T2 , there is no possibility that an erroneous output signal will be latched.

On the other hand, in an LSI to which the conventional wiring system as shown in FIG. 2 is applied, noise n is generated at the output B of the output buffer _1b , which operates at different timings due to the influence of changes in the outputs of the output buffers 1a 1 to 1an. Therefore, if the latch timing of this output B matches the change timing T of the output buffers _A1 to An, the circuit receiving the output B may latch an incorrect output signal or malfunction due to the noise of the output B. There is a risk that you may be

On the other hand, according to the wiring method of the above embodiment,
Since the power supply wiring for the output buffers 1a ₁ ~ 1an and 1b ₁ ~ 1bm are separate, the output buffers _1a 1 ~ 1an and 1b 1 ~ 1bm are wired separately.
Output buffer 1b ₁ to 1 due to 1an output change
For example, only a very small noise n'' is generated in the outputs _B1 to Bm of bm due to the impedance component of the common power supply pin, so even if output B is latched at timing T, there will be no erroneous data. will not be latched.Also, even if there is a circuit that receives output B and uses it to latch, there is no risk of erroneously latching due to small noise n''.

As can be seen from the above explanation, the best way to divide the power supply wiring is to divide it into output buffers whose outputs are latched at different timings or operated at different timings.
However, output buffers whose outputs are usually latched or operated at different timings are often operated by signals (clocks) at different timings, so they are operated by clocks at different timings as in the above embodiment. The power supply wiring can be divided for each output buffer.

In this way, by separating the power supply wiring for each output buffer with different timing, malfunctions can be reliably prevented.

Note that if there are three or more groups of output buffers with different output timings, the power supply wiring may be divided accordingly.

Next, as a more specific example, the present invention will be described.
We will explain how to divide the power supply wiring when applied to an ACRTC (advanced CRT controller) LSI that constitutes a graphic display system equipped with a CRT display device.

FIG. 5 shows a block diagram of the ACRTC. The ACRTC of this embodiment includes a system bus interface circuit 11 that interfaces with a microprocessor (not shown), and a refresh memory and frame bus that store display image data on a CRT display device. A CRT interface circuit 12 interfaces with an image memory called a buffer (not shown), a drawing processor 13 interprets commands from the microprocessor and performs drawing processing on the image memory, and displays on the CRT. The display processor 14, which calculates the display address of the frame buffer, and the display device, such as the horizontal and vertical synchronization signals HSYNC and VSYNC, and the timing of screen division, according to the screen format to be
A timing processor 15 generates timing signals for each circuit block within the ACRTC. Although not particularly limited, each of the drawing processor 13, display processor 14, and timing processor 15 is a microprogram ROM (read-only memory).
independently controlled by control information written in
Parallel processing is becoming possible.

Also, within the ACRTC above, there is a DMA (not shown)
(direct memory access) between the main memory on the system side and the controller.
Also provided are a DMA control circuit 16 that generates appropriate control signals when performing DMA transfer, and an interrupt control circuit 17 that generates interrupt signals for the microprocessor.

The ACRTC with the above configuration uses a system data bus (D ₀ to
_D15 ) connected to the microprocessor via
via the same 16-bit wide frame buffer address/data bus (MAD ₀ to MAD ₁₅ ) and the 5-bit wide memory or raster address bus (MA ₁₆ to ₁₉ /RA ₀ to ₃ and RA ₄ ). It is connected to the frame buffer and refresh memory.

Therefore, ACRTC receives drawing commands and their parameters from the microprocessor,
When supplying internal register information to the microprocessor, the system data bus (D ₀ to D ₁₅ )
16 input/output buffers connected to are operated simultaneously. Also, when driving the image memory,
More than 20 output buffers connected to frame buffer address/data buses (MAD ₀ to _{MAD 15} ) are operated simultaneously.

The ACRTC has five types of clocks inside, including an output buffer on the microprocessor side, an output buffer on the image memory side, and an output buffer for outputting various control signals such as horizontal and vertical synchronization signals. are operated at different timings.

Therefore, in this embodiment, the output buffer in ACRTC is connected to the system data bus (D ₀ to _{D 15} ).
Output buffer group and frame buffer address/data bus (MAD ₀ to MAD ₁₅ )
It is divided into three groups: an output buffer group that outputs to the memory or raster address bus (MA ₁₆ to ₁₉ /RA ₀ to ₃ and RA ₄ ), and an output buffer group that outputs various control signals. Corresponding power pads are provided, and separate power wires are drawn from each power pad to supply the power supply voltage Vss to each output buffer.

This allows the image memory interface side to
More than 20 output buffers are operated to prevent the control signal and the low level output of the output buffer on the system data bus side from floating even if the outputs change at the same time.

In addition, in the embodiment of FIG. 5, DREQ,
DONE, is indicated by
Control signals supplied from ACRTC to the microprocessor side, ,MRD,CHR,1,2,
HSYNC, , 1, 2 are control or timing signals supplied from the ACRTC to the CRT display side.
is the reset signal for ACRTC, CLOCK and
MCYC is the clock input/output to ACRTC.

Also, RS, R/ are control signals supplied to the ACRTC from the microprocessor side, and LPSTB is a control and timing signal supplied to the ACRTC from the CRT display side.

In the above embodiment, a case has been described in which the power supply wiring is applied to the ground potential Vss side, which has a relatively small margin, but the power supply wiring that supplies the power supply voltage Vcc to each output buffer is similarly applied to each output buffer with a different timing. By installing a power supply pad and dividing the power supply wiring, it is possible to prevent the generation of noise that appears in the high level of the output.
more effective.

Furthermore, in the above embodiment, the power supply wiring and power supply pads are divided for each output buffer with different timing, but if the power supply pins that supply the power supply voltage to the power supply pads are similarly divided and provided with a plurality of them, the effect will be even more effective. It is true.

Furthermore, even if the output buffers have the same timing, if the power supply wiring cannot be shared in common due to layout considerations, they may be divided and arranged.

[Effect] Since the power supply wiring is divided for each output buffer with different timing and the power supply voltage is supplied, when the output signal of an output buffer with a certain timing is latched, the output change of another output buffer with a different timing is changed. This prevents noise from being generated, which prevents the LSI that receives the output from latching erroneous data, and prevents the LSI that has a circuit for latching the output from malfunctioning. effective.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, only the power supply wiring may be divided into output buffers with different timings, and the power supply pads may be shared. Furthermore, in the above embodiment,
Although a case has been described in which the present invention is applied to power supply wiring to an output buffer through which a particularly large current flows, it is also possible to similarly apply the present invention to power supply wiring to internal circuits.

[Field of Application] The above explanation mainly describes the invention made by the present inventor and the logic behind the invention.
Although the description has been made regarding the application to LSI, the present invention is not limited thereto, and can be used for semiconductor integrated circuits in general.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of a power wiring system in a semiconductor integrated circuit device according to the present invention, FIG. 2 is an explanation showing a conventional general power wiring system, and FIG. FIG. 4 is a waveform diagram showing the output state of the output buffer when the present invention is applied, and FIG. 5 is a waveform diagram showing the output state of the output buffer when the present invention is applied. FIG. 2 is a block diagram showing a configuration example of an ACRTC as an example of the obtained LSI. 1a ₁ ~ 1an, 1b ₁ ~ 1bm, 1b... Output buffer, 2a, 2b, 2... Power supply pad, 3a, 3
b, 3...Power wiring, 11...System bus
Interface, 12...CRT interface,
13...Drawing processor, 14...Display processor, 15...Timing processor, 16...
DMA control circuit, 17... interrupt control circuit.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit device having a plurality of output buffers with different output timings, separate power supply wiring is provided in which at least one of the power supply voltages of the circuit is divided for each of the output buffers with different output timings. A semiconductor integrated circuit device, characterized in that it is supplied by. 2. The semiconductor integrated circuit device according to claim 1, wherein the divided power supply wirings are each connected to separate power supply pads. 3. The semiconductor integrated circuit device according to claim 2, wherein the plurality of power supply pads are each connected to separate external pins. 4. In a semiconductor integrated circuit device having a plurality of clocks with different phases or periods, and an output buffer whose output is operated at different timings depending on the clock, a separate power supply wiring is connected to the output buffer for each clock to be operated. A semiconductor integrated circuit device according to claim 1, 2, or 3, characterized in that a power supply voltage is supplied to the semiconductor integrated circuit device. 5. In a semiconductor integrated circuit equipped with a plurality of bus interface circuits operated by clocks with different timings, a power supply voltage is supplied to the output buffer through a separate power supply wiring for each bus interface circuit. 5. A semiconductor integrated circuit device according to claim 4, characterized in that: