JPH0434846B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a circuit for indicating tuning instructions, antenna input level (received electric field level), etc.

BACKGROUND TECHNOLOGY AND PROBLEMS For example, a circuit as shown in FIG. 1 has been considered as a tuning instruction and antenna input level instruction circuit in an FM receiver.

That is, in FIG. 1, 1 to 3 indicate front-stage, middle-stage, and rear-stage FM intermediate frequency amplifiers, and the middle-stage intermediate frequency amplifier 2 is composed of, for example, two differential amplifiers 21 and 22. That is, the emitters of transistors Q ₁ and Q ₂ are connected to a common resistor R ₁ , and the collectors are connected to resistors R ₂ and R ₃ (R ₂ = R ₃ ).
A differential amplifier 21 is configured by connecting the differential amplifier 21 to the power supply terminal T through the transistors Q ₁₁ and Q ₁₂ and supplying a bias voltage to the base thereof through the resistors R ₈ and R ₉ .

In addition, transistors Q ₇ , Q ₈ and resistors R ₁₁ ~
A differential amplifier 22 is similarly configured by R ₁₃ , and intermediate frequency signals having mutually opposite phases are supplied from the intermediate frequency amplifier 1 to the amplifier 3 through the amplifiers 21 and 22 .

Further, resistors R ₄ and R ₅ (R ₄ = R ₅ ) are connected in series between the collectors of transistors Q ₁ and Q ₂ , and the connection midpoint P is in contact with the base of transistor Q ₃ .
Its emitter is connected to the terminal T through the resistor _R6 , and the transistor _Q4 and the resistor _R7 ,
R ₁₄ and R ₁₅ are similarly connected to amplifier 22.

The collectors of transistors Q ₃ and Q ₄ are connected to the collector of transistor Q ₅ , and
The ground is the reference potential point, and the transistor _Q5
A current mirror circuit 23 is constituted by transistors Q ₅ and Q ₆ with
For example, a level meter M is connected to the collector of _Q6 .

In such a configuration, as shown in FIG. 2A, the base voltages of transistors Q ₁ and Q ₂ are set to V _B1 ,
V _B2 is the collector current, I _C1 and I _C2 are the collector currents, V ₀ is the base voltage when there is no signal, and I ₀ is the collector current when there is no signal.

Then, voltages V _B1 and V _B2 change complementarily, but when voltage V _B1 increases and voltage V _B2 decreases, current I _C1 increases correspondingly, and the current
I _C2 decreases. That is, V ₀ ≦V _B1 <V ₀ +ΔVa,
When V ₀ −ΔVa<V _B2 ≦V ₀ , the original operation as a differential amplifier is performed, and the currents I _C1 and I _C2 are
It is proportional to V _B1 and V _B2 , and I _C1 + I _C2 = 2I ₀ .

Then, V ₀ +ΔVa≦V _B1 <V ₀ +ΔVb, V ₀ −
When ΔVb＜V _B2 ≦V ₀ −ΔVa, the transistor
Q ₂ is cut off and I _C2 =0, and as a result, the transistor Q ₁ operates simply as a transistor with its emitter grounded, so that the current I _C1 is proportional to the voltage V _B1 and its slope is gentle.

Furthermore, when V ₀ +ΔVb≦V _B1 and V _B2 ≦V ₀ −ΔVb, transistor Q ₂ is cut off and I _C2 = 0.
, transistor Q ₁ is turned on,
The current I _C1 becomes a constant value.

Since the relationship between the voltages V _B1 and V _B2 and the currents I _C1 and I _C2 is symmetrical with respect to the voltage V ₀ , the characteristics are as shown in FIG. 2A. Therefore, the intermediate frequency signal Ei with the voltage V ₀ at the DC level is applied to the transistors Q ₁ and Q ₂
If they are supplied in opposite phases to each other, this will not only be amplified, but also have a limiting effect.

And the collector current of transistors Q ₁ and Q ₂
Since I _C1 and I _C2 change in this way, their collector voltages V _C1 and V _C2 will change as shown by the solid line in Figure 2B, and the voltage Vp at point P will change as shown by the solid line in Figure 2B.
Since Vp=1/2 (V _C1 +V _C2 ), the voltage Vp changes as shown by the broken line in FIG. 2B. That is, when the instantaneous value of the intermediate frequency signal Ei is less than or equal to ΔVa, it is constant at Vp=Vc.c.−V _D , but when it is greater than or equal to ΔVa and less than or equal to ΔVb, the voltage Vp changes in accordance with the signal voltage Ei. Further, when the voltage is ΔVb or more, the voltage Vp remains constant. Note that the voltage V _D is
It can be set arbitrarily by resistors _R1 to _R5 .

Since this voltage Vp is supplied to the transistor _Q3 , if the threshold level at which the transistor _Q3 is turned on is set to the voltage _VD ,
The collector current I _C3 of transistor Q ₃ is equal to the signal voltage
It changes with respect to Ei as shown by the solid line in Figure 2C, and when Ei < ΔVa, I _C3 = 0, ΔVa
When ≦Ei≦ΔVb, it is proportional to the voltage Ei, and Ei>
When ΔVb, it becomes a constant value.

This current I _C3 is supplied to the transistor Q ₅ , and since the transistors Q ₅ and Q ₆ constitute a current mirror circuit 23, the meter M
A current equal to the current I _C3 flows through.

Therefore, the amplifier 21 and the transistor _Q3 cause the meter M to swing as shown by the solid line in FIG. 2C with respect to the signal voltage Ei. In addition,
In this case, a low-pass filter is configured by the resistors R ₄ and R ₅ and the input capacitance of the transistor Q ₃ , and the intermediate frequency component is removed due to the high frequency characteristics of the transistor Q ₃ , so that the current I _C3 becomes a direct current.

The same operation is performed by the amplifier 22 and the transistor _Q4 , and in the amplifier 22, the signal level is large by the gain of the amplifier 21, so the collector current I _C4 of the transistor _Q4 is equal to the signal voltage. It changes with respect to Ei as shown by the broken line in FIG. 2C. Then, since the current I _M which is the sum of the currents I _C3 and I _C4 flows through the meter M, the deflection of the meter M becomes as shown by the chain line in FIG. 2C.
Therefore, the meter M indicates the input signal level (received electric field level).

In this way, according to the circuit of FIG. 1, it is possible to indicate the level of the input signal, but in this case, especially according to this indicating circuit, the signal voltage Ei exceeds the dynamic range (V ₀ ±ΔVa) of the amplifier 21. Since the voltage change that occurs at the time, that is, the saturation component, is extracted and used to indicate the input level, no loss occurs in the amplifier 21. In addition, the configuration is simple, and when converting the intermediate frequency amplifier into an IC,
It can be integrated with IC.

Furthermore, when converting into an IC, no external components are required, making it suitable for IC conversion.

Furthermore, when the input signal level is low and unsuitable for reception, Ei < ΔVa and the meter M will not swing. In other words, the meter M will not swing even for signals that are not suitable for reception. There is no.

However, in this instruction circuit, the transistor
If the current amplification factor h _FE of Q ₁ , Q ₂ (and Q ₇ , Q ₈ ) varies, the collector currents I _C1 , I _C2 vary, and the meter current I _M also varies as shown in FIG. 3. In particular, in ICs, the variation in the current amplification factor h _FE is large, so the variation in the meter current I _M is also large.

Purpose of the Invention This invention attempts to solve these problems.

SUMMARY OF THE INVENTION Therefore, in the present invention, variations in the collector currents of the transistors Q ₁ , Q ₂ , Q ₇ , and Q ₈ are corrected using pinch resistors.

Embodiment That is, in FIG. 4, the middle-stage intermediate frequency amplifier 2 is configured in the same manner as in FIG. 1, and the current line to the meter M is also configured in the same manner.

Further, the bases of transistors Q ₂₁ and Q ₂₂ are connected to each other and to the collector of transistor Q ₂₁ , whose emitter is connected to power supply terminal T through resistor R ₂₁ , and the emitter of transistor Q ₂₂ is connected to resistor R. A current mirror circuit 24 is constructed, which is connected to the terminal T through a parallel circuit of ₂₂ and R ₂₃ , with the terminal T serving as a reference potential point, and with the transistor Q ₂₁ serving as the input side.

In this case, the resistor R ₂₃ is a pliers resistor. That is, when this indicating circuit is integrated into an IC, a transistor structure is formed, and electrodes are formed on both sides of the base region, and between these electrodes, a transistor structure is formed. The resistance of the base region is the resistor _R23 . Note that the resistor _R22 is a general diffused resistor.

Furthermore, between the collector of the transistor Q ₂₁ and the ground, the collector-emitter of the transistor Q ₂₃ and the resistor R ₂₃ are connected in series.
The base of Q ₂₃ is connected to the bias power supply V. Further, a diode-connected transistor Q ₁₁ is connected between the collector of the transistor Q ₂₂ and the ground.
Q ₁₂ is connected in series and transistor Q ₂₂
The voltage V _C11 obtained at the collector of the transistor
It is supplied as a bias voltage to Q ₁ , Q ₂ , Q ₇ , and Q ₈ .

According to such a configuration, a constant collector current I _C23 flows through the transistor Q ₂₃ , and this collector current I _C23 becomes the input current of the current mirror circuit 24, so the transistor Q ₂₂ has a current I _C23 as a reference. , and a collector current I _C22 of a constant magnitude determined by the values of the resistors R ₂₁ to R ₂₃ flows. and,
This current I _C22 flows through the transistors Q ₁₁ and Q ₁₂ , so at this time, the voltage V _C11 is applied to the transistors Q ₁₁ and Q ₁₂ .
is obtained, and this voltage V _C11 is supplied as a base bias to transistors Q ₁ and Q ₂ through resistors R ₈ and R ₉ .

Now, when this instruction circuit is converted into an IC,
Assume that the current amplification factors h _FE of transistors Q ₂ and Q ₂ vary and are larger than a reference value. Then, the collector currents I _C1 and I _C2 of the transistors Q ₁ and Q ₂ should become larger than the reference value.

However, in IC, the current amplification factor of the transistor
h Since the variation between _FE and pinch resistance is proportional,
In this case, the resistor (pinch resistor) _R23 also has a value larger than the reference value.

Therefore, the collector current of transistor _Q22 I _C22
becomes smaller than the reference value, and the voltage V _C11 becomes lower than the reference value, so the collector currents I _C1 and I C2 of the transistors Q ₁ and Q ₂ decrease, and the collector current I _C1 due to the increase in the current amplification factor _{h FE} decreases. , the increase in I _C2 is offset.

Also, conversely, the current amplification factor of transistors Q ₁ and Q ₂
If h _FE fluctuates smaller than the standard value, then
The collector currents I _C1 and I _C2 should be smaller than the reference value.

However, at this time, the resistor (pinch resistor)
Since the value of _R23 becomes smaller than the reference value, the collector current I _C22 becomes larger than the reference value and the voltage V _C11
becomes larger than the reference value, and therefore the collector currents I _C1 and I C2 of the transistors Q ₁ and Q ₂ increase, and the decrease in the collector currents I _C1 and _{I C2 due} to the decrease in the current amplification factor h _FE is canceled out. .

Note that the same applies to variations in the current amplification factors h _FE of the transistors Q ₇ and Q ₈ . Further, the amount of cancellation when the variations in the collector currents I _C1 and I _C2 are canceled can be adjusted by the resistor R ₂₂ .

Thus, according to the invention, the transistor
Even if the current amplification factors h _FE of Q ₁ and Q ₂ vary, the collector currents I _C1 and I _C2 can be corrected to the reference values, so that, for example, the deflection characteristics of the meter M can be made constant.

Moreover, in this case, especially according to the present invention, it is only necessary to add a few elements, which does not hinder implementation of IC. Also, there is no need to consider cost increases.

Effects of the Invention Even if the power supply amplification factors of the transistors vary, constant indicating characteristics can be obtained. Furthermore, the configuration is simple and is advantageous for IC implementation.

[Brief explanation of drawings]

1 to 3 are diagrams for explaining this invention, and FIG. 4 is a connection diagram of an example of this invention. 1 to 3 are respective stages of the intermediate frequency amplifier.

Claims (1)

[Claims] 1 The collectors of the first and second transistors are connected to one end of the power supply through first and second resistors, and the emitters of the first and second transistors are connected to the other end of the power supply through a common resistor. supplying an input signal between the bases of the first and second transistors, and supplying the collector output of the first or second transistor to the indicating means through a circuit having a predetermined threshold level; When the level of the input signal exceeds the dynamic range of the first and second transistors, the level of the input signal is indicated by the indicating means, and a pinch resistor is connected to the emitter of the third transistor. A level indicating circuit that converts the collector current of the third transistor into a voltage and supplies this voltage to the bases of the first and second transistors as a bias voltage.