JPH04348611A - Pulse generating circuit - Google Patents

Abstract

PURPOSE:To control and adjust a time zone when an output pulse signal is active and a time zone when an output pulse signal is inactive corresponding to fluctuation of a power supply voltage in the pulse generating circuit from which a polyphase pulse signal is generated. CONSTITUTION:A level fluctuation of a power supply voltage is detected by a power supply voltage detection circuit 13 and inputted to a gate of an N- channel MOSFET 7. A P-channel MOSFET 4 and an N-channel MOSFET 5 are used for components of an inverter or the P-channel MOSFET 4 and the N-channel MOSFETs 5, 6, 7 are used for components of the inverter are decided depending on the state of on/off of the N-channel MOSFET 7. Thus, the path of an input signal phi is selected to any of the component paths for determining the delay characteristic of the semiconductor circuit components with respect to the input signal phi depending on high or low power supply voltage. The high level state of an output signal phiB shares much in the time zone when the power supply voltage is lowered, and the time zone when both output signals phiA and phiB are at a low level is longer when the power supply voltage gets higher.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a pulse generation circuit,
In particular, the present invention relates to a pulse generation circuit that outputs a plurality of pulse signals having mutually different active periods in response to one pulse signal input.

0002

2. Description of the Related Art A circuit diagram of a conventional pulse generating circuit of this type is shown in FIG. Also, shown in FIG. 4 is a timing diagram showing the operation of this conventional pulse generating circuit.

As shown in FIG. 3, this pulse generating circuit is composed of inverters 14 and 17 to 21 and NAND circuits 15 and 16, and when the input signal φ is at a high level, the output signal φA is high. The output signal φB is at a low level.

When the input signal φ changes from high level to low level, the output signal φA changes to the NAND circuit 15.
The output signal φB changes to a low level with a delay of time T1 through the signal propagation time of the inverter 17 and the inverter 18, 19, and 20.
Through the signal propagation time by the ND circuit 16, the output signal φ
A is further delayed by time T2 and changes to high level. Similarly, when input signal φ changes from low level to high level, output signal φB changes to low level with a delay of time T1, and output signal φA goes high with a further delay of time T2 from output signal φB. Change in level. The timing relationship between the input signal φ and the output signals φA and φB in this case is as clearly shown in the timing diagram of FIG.

As described above, in the conventional pulse generation circuit, the output signals φA and φB both maintain a low level state during the time period T2 in response to the input signal φ, and the output signals φA and φB both maintain a low level state during time period T2. It never reaches a high level.

[0006]

In the conventional pulse generating circuit described above, when the output signal is used as a control signal for another logic circuit, if the time period in which both output signals are not active is made long, When the active period of the output signal becomes short and the power supply voltage is low, it becomes difficult to operate the logic circuit at a high frequency.

Conversely, if the period in which both output signals are not active becomes shorter, due to the transient characteristics within the logic circuit, there will be a period in which the output signals of the pulse generation circuit are both active within the logic circuit. become. In this case, as the power supply voltage increases, the signal propagation time of the transistors that make up the logic circuit becomes shorter, so malfunctions such as data throughput occur in the logic circuit during the period when both of the aforementioned output signals are active. do.

As described above, in the conventional pulse generating circuit, when the output signal is used as a control signal for another logic circuit, during low voltage operation, the time period in which both output signals are not active is shortened, During high-voltage operation, there is a drawback that contradictory conditions are required, such as it is better to lengthen the period during which both output signals are inactive.

[0009]

[Means for Solving the Problems] The pulse generating circuit of the present invention receives an input pulse signal and utilizes the delay characteristics caused by the signal propagation time of semiconductor circuit elements, so that the time periods in which they are mutually active are set. A pulse generation circuit that generates and outputs a plurality of different pulse signals includes a power supply voltage detection circuit that detects level fluctuations in the power supply voltage and outputs a predetermined level detection signal; and means for appropriately switching and controlling delay characteristics caused by signal propagation time of the semiconductor circuit element with respect to the input pulse signal.

0010

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment includes inverters 1, 3, 8, and 10 to 12, NAND circuits 2 and 9, P-channel MOSFET 4, and N-channel MOSFET 4.
It is configured to include SFETs 5 to 7 and a power supply voltage detection circuit 13. Furthermore, FIGS. 2A and 2B are timing diagrams of input and output signals showing the operation of this embodiment.

In FIG. 1, when the power supply voltage is high,
The power supply voltage level is detected in the power supply voltage detection circuit 13, and the output of the power supply voltage detection circuit 13 is outputted at a low level and inputted to the gate of the N-channel MOSFET 7. As a result, N-channel MOSFET 7 is turned off, only P-channel MOSFET 4 and N-channel MOSFET 5 are put into operation, and an inverter is configured by these MOSFETs.

Therefore, when the input signal φ is at a high level, the output signal φA is at a high level and the output signal φB is at a low level, and when the input signal φ changes to a low level, the output signal φA is output from the NAND circuit 2 and the inverter 3. The output signal φB becomes low level after a delay of time T1 through the signal propagation time of NAND circuit 9, inverters 8 and 9, and P channel MOSFET
The output signal φA is
After a further delay of time T2, the signal becomes high level. Similarly, when the input signal φ changes from a low level to a high level, the output signal φB becomes a low level with a delay of time T1, and the output signal φA becomes a high level with a further delay of a time T2 from the output signal φB. At this time, the time period in which the output signals φA and φB are individually at a high level is a time period T3, as shown in FIG. 2(a).

Next, when the power supply voltage is low, the output of the power supply voltage detection circuit 13 becomes high level, and N
Channel MOSFET 7 is turned on, and P-channel MOSFET 4 and N-channel MOSFETs 5, 6, and 7 constitute an inverter. This inverter has characteristics that the ability to change the output to a low level is improved and the signal propagation time is short compared to the above-described case where the power supply voltage is a high voltage. The timing relationship among the input/output signals φ, φA and φB in this case is as shown in FIG. 2(b). That is, when the input signal φ changes from high level to low level, the delay time T2a of the output signal φB with respect to the output signal φA becomes smaller than the delay time T2 due to the shortening of the signal propagation time of the inverter described above. The time period T3a in which the output signal φB is at a high level is the time period T3a.
becomes larger than

With the above operation, when the power supply voltage decreases, the output signal φB is kept at a high level for a longer period of time, and when the output signals φA and φB are used as control signals for other logic circuits, , it is possible to facilitate operation at higher frequencies, and when the power supply voltage becomes high, the time period in which both output signals φA and φB are at a low level is lengthened, thereby preventing the above-mentioned logic circuit from malfunctioning. becomes possible.

[0016]

As explained above, the present invention is capable of switching the active time period of an output pulse signal in response to fluctuations in power supply voltage in a pulse generation circuit that generates a plurality of mutually different pulse signals. By controlling this pulse signal, when this pulse signal is used as a control signal for another logic circuit, there is an effect that the operating power supply voltage range of the logic circuit can be expanded and a more stable function can be exhibited.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of signals showing the operation of this embodiment.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a timing chart of signals showing the operation of the conventional example.

[Explanation of symbols]

1, 3, 8, 10-12, 14, 17-21 Inverter 2, 9, 15, 16 NAND circuit 4 P
Channel MOSFET 5 to 7 N-channel MOSFET 13 Power supply voltage detection circuit

Claims (1)

[Claims] 1. A pulse that receives an input pulse signal and generates and outputs a plurality of pulse signals that are mutually active in different time periods by utilizing the delay characteristics caused by the signal propagation time of a semiconductor circuit element. The generation circuit includes a power supply voltage detection circuit that detects level fluctuations in the power supply voltage and outputs a predetermined level detection signal, and a signal propagation of the semiconductor circuit element in response to the input pulse signal in response to the input of the level detection signal. A pulse generation circuit comprising means for appropriately switching and controlling delay characteristics caused by time.