JPH0583111A - Cmos integrated circuit - Google Patents

Abstract

PURPOSE:To realize the CMOS integrated circuit which is designed without consideration of a metal skew and a dispersion in a function block due to fluctuation in temperature and power supply voltage and a transistor(TR) characteristic difference at manufacture. CONSTITUTION:The CMOS integrated circuit provided with a buffer 5 and flip-flops 2, 4 or the like forming a function block is provided with a memory 7 rewritten externally and storing a prescribed control setting value inputted externally and drive capability variable circuits 3, 6 inserted and connected to a signal path including the function block, receiving the control setting value outputted from the memory 7 and controlling and adjusting the drive capability of the function block.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS integrated circuit, and more particularly to a CMOS integrated circuit whose internal drive capability can be controlled from the outside.

[0002]

2. Description of the Related Art A functional block in a conventional CMOS integrated circuit has means for stabilizing a change in delay time due to a change in temperature and a power supply voltage and a change in delay time due to a difference in transistor characteristics during manufacturing of a semiconductor integrated circuit. , Are being studied in various ways.

FIG. 3 is a circuit diagram showing an example of a conventional CMOS integrated circuit. As shown in FIG. 3, flip-flops 24 and 25 and a buffer 26 are provided. In the case of this example, the delay times in the paths 201 and 202 are calculated corresponding to the input signals 106 and 107, respectively, and it is examined whether or not the circuit operates stably in any state. There is a need.

FIGS. 4A, 4B and 4C are shown in FIG.
6 is a timing chart for explaining the operation of the MOS integrated circuit in FIG. Figure 4 (a), (b) T 1 and T ₂ are shown in and (c), variations in temperature and supply voltage, the function block by the transistor characteristic difference at the time of manufacture of the semiconductor integrated circuit, i.e. a flip-flop 24 buffer 26 shows a variation range of the delay time of 26, and there is a possibility that the circuit may malfunction due to the overlapping of T ₁ and T ₂ depending on the change of the timings at the nodes B and C. If there is a risk that the circuit may malfunction, it may be possible to insert a delay block into the path 201 or the path 202 in consideration of a sufficient margin for delay time variations.

FIG. 5 is a circuit diagram showing another CMOS integrated circuit based on such an idea. Flip-flops 27 and 29, as shown in FIG.
The delay circuit 28 and the buffer 30 are provided. In this conventional example, the delay circuit 28 is inserted and connected between the flip-flops 27 and 29, which makes it possible to shift the timing at the node B in FIG. FIGS. 6A, 6B and 6C are timing charts showing the circuit operation in FIG. 5, and the delay circuit 28 having a sufficient delay time is inserted in the path 203 with respect to the path 204. Therefore, the timing T ₁ at the node B is equal to the timing T _{2 at the} node C.
The flip-flop 29 can always maintain stable operation without being influenced by the timing due to the variation in the delay time of the flip-flop 29.

Further, with the technical innovation of the semiconductor process (miniaturization of the process), the problem of metal skew has become remarkable. FIG. 7 is a circuit diagram of a CMOS integrated circuit showing an example of such a conventional defect. As shown in FIG. 7, in this conventional example, the flip-flops 31 and 3 are provided.
2 and the buffer 33. As a result of the arrangement and wiring of each component, the wiring length between the buffer 33 and the node D is L ₁ , up to the node D and the clock terminal of the flip-flop 32 (corresponding to the node G). Is L ₂ , the wiring length between the node D and the clock terminal of the flip-flop 31 (corresponding to the node E) is L ₃ , and the wiring length L ₂ is sufficiently larger than the wiring length L _3. , A malfunction occurred in the circuit.

FIGS. 8 (a), (b), (c), (d) and (e) are timing charts showing the circuit operation in FIG. 7, but the wiring length L ₂ is the wiring length. Since the length L ₃ is sufficiently larger than the length L ₃ , the rise time difference T _{3 at} the node E and the node G becomes large, which causes the hold time T ₄ (Note: the time period before the hold time T ₄ of the flip-flop 32 to be increased. When the data changes, the circuit will not operate stably) and the time will run short, resulting in circuit malfunction.

[0008]

DISCLOSURE OF THE INVENTION The conventional CMO described above
In the S integrated circuit, it is examined whether or not the circuit operates stably depending on the variation in the delay time of the functional block, and for a circuit which may cause malfunction, a delay circuit considering a sufficient margin. Should be inserted
There is a drawback that the circuit design is difficult and complicated, and for the metal skew problem that became prominent with the technological innovation of the semiconductor process, after placement and routing, check the wiring length and delay time of each. If there is a risk of causing a circuit malfunction due to metal skew, the placement and routing will be repeated until the circuit malfunction due to the metal skew disappears. There is a drawback in that there is a problem in circuit design that a delay circuit is inserted in consideration of a sufficient margin so as not to occur.

[0009]

A CMOS integrated circuit of the present invention is a CMOS integrated circuit provided with predetermined functional blocks.
In the integrated circuit, a control memory that can be rewritten from the outside and that stores a predetermined control setting value input from the outside, and is inserted and connected to a signal path including the functional block, And a drive capacity variable circuit that receives and outputs the control set value that is output and controls and adjusts the drive capacity of the functional block.

In the variable drive capacity circuit, at least a source is connected to a high-potential-side power supply, and a gate is connected to a first output terminal of the control memory, and a first P-channel MOS transistor, A source is connected to the drain of the first P-channel MOS transistor, an inverted signal of a predetermined input signal is input to the gate, a reinverted signal of the inverted signal is input to the drain, and an output terminal is connected. A second P-channel MOS transistor, and a first N-channel drain connected to the drain of the second P-channel MOS transistor and a gate connected to the gate of the second P-channel MOS transistor.
A channel MOS transistor, a first inverter whose input end is connected to the first output terminal of the control memory, a drain is connected to the source of the first N-channel MOS transistor, and a gate is the first A second N-channel MOS transistor connected to the output end of the inverter of which the source is connected to the power source on the low potential side, and the source is connected to the power source on the high potential side, and the gate is the second of the control memory. Third P-channel MO connected to the output terminal of the
The S transistor and the source are the third P channel MO.
A fourth P-channel MOS transistor connected to the drain of the S-transistor, the gate of which receives an inverted signal of a predetermined input signal, the drain of which receives the re-inverted signal of the inverted signal and the output terminal of which is connected. And a drain connected to the drain of the fourth P-channel MOS transistor, and a gate connected to the fourth P-channel MOS transistor.
Third N channel M connected to the gate of the transistor
An OS transistor, a second inverter whose input end is connected to the second output terminal of the control memory, a drain is connected to the source of the third N-channel MOS transistor, and a gate is the second The fourth, which is connected to the output terminal of the inverter and whose source is connected to the low-potential-side power supply.
And an N-channel MOS transistor of.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. As shown in FIG. 1, the CMOS integrated circuit 1 of this embodiment includes flip-flops 2 and 4, drive capacity variable circuits 3 and 6, a buffer 5, and a memory 7, and The internal configuration of the drive capability variable circuit 6 is shown together with the internal configuration of the buffer 5 in FIG.

In FIG. 1, the input signal 101 is input to the D terminal of the flip-flop 2, and the output signal of the Q terminal thereof is input to the drive capacity variable circuit 3. Also, input signal 1
02 is input to the variable drive capacity circuit 6 via the buffer 5, while the input signal 103 is input to the memory 7 that can be freely rewritten from the outside, and the input signal 103 is input to the memory 7. In response, control signals are output from the terminals of Q ₁ , Q ₂ , Q ₃ and Q ₄ , respectively, and are input to the corresponding drive capacity variable circuits 3 and 6. As is clear from this, in the present invention, the buffer 5
The drive capability in the signal path including the drive capacity varying circuit 6 and the drive path in the signal path including the flip-flop 2 and the drive capacity varying circuit 3 can all be freely controlled from outside the semiconductor integrated circuit via the memory 7. ..

FIG. 2 is a circuit diagram showing the internal structure of the buffer 5 and the drive capacity varying circuit 6 shown in FIG.
Corresponding to, buffer 5 is configured to include an inverter 8 including P-channel MOS transistor 9 and N-channel MOS transistor 10 and an inverter 11 including P-channel MOS transistor 12 and N-channel MOS transistor 13, and also driven. Variable capacity circuit 6
Comprises inverters 14 and 19, P channel MOS transistors 15, 16, 20 and 21, and N channel MOS transistors 17, 18, 22 and 23.

The operation at the time when the temperature, the power supply voltage and the general conditions of the transistor characteristics at the time of manufacturing the semiconductor integrated circuit are set will be described below.

First, when the temperature, the power supply voltage, and the transistor characteristics during manufacturing are in a steady state, Q ₁ in the memory 7 is
When the output level is set to the low level and the Q ₂ output level is set to the high level, the P-channel MOS transistor 15
And the N channel MOS transistor 18 are turned on, and the P channel MOS transistor 20 and the N channel M transistor are turned on.
The OS transistor 23 is turned off, and the inverter 1
1, P-channel MOS transistor 16 and N-channel MOS transistor 17 are in a state of having an output signal from inverter 8. Here, the input signal 102
Is input at a high level, a low level signal is output from the inverter 8 and a high level signal is output as an output signal 104 via the inverter 11 and the P channel MOS transistors 15 and 16.

Next, the temperature rises and the power supply voltage falls,
When both the Q ₁ output and Q ₂ output levels in the memory 7 are set to a low level when the transistor characteristics are slow, P channel MOS transistors 15 and 20 and N channel MOS transistors 18 and 2 are set.
3 are both turned on, and the inverter 11, the P channel MOS transistors 16 and 21, the N channel MOS
The transistors 17 and 22 are in a state of having an output signal from the inverter 8. Here, the input signal 10
When 2 is input at a high level, a low level signal is output from the inverter 8 and is output via the inverter 11, the P channel MOS transistors 15 and 16, and P
Via channel MOS transistors 20 and 21,
A high level signal is output as the output signal 104.

Next, the temperature drops and the power supply voltage rises,
If the Q ₁ output and the Q ₂ output in the memory 7 are both set to the high level in the state where the transistor characteristics are fast, the P channel MOS transistors 15 and 20 and the N channel MOS transistors 18 and 2 are set.
3 is turned off, and the inverter 11 is in a state of having an output signal from the inverter 8. Here, when the input signal 102 is input at a high level, a low level signal is output from the inverter 8 and the inverter 1
At the output of 1, a high level signal is output as the output signal 104.

As described above, the drive capability of the drive capability variable circuit 6 is controlled by appropriately setting the level state in the memory 7 in accordance with the temperature, power supply voltage, and variations in transistor characteristics during the manufacture of semiconductor integrated circuits. It becomes possible to do.

Next, let us consider an assumed example in which such a drive capacity variable circuit is applied to the conventional circuit shown in FIG. In FIG. 7, when the wiring length L ₂ is sufficiently longer than L ₃ , a circuit malfunction due to metal skew occurs. A countermeasure against this will be described.
First, it is assumed that the drive capability variable circuit is inserted in the signal paths of the buffer 33 and the flip-flop 31. In this case, it is assumed that the drive capability variable circuit inserted in the signal path of the buffer 33 is set in the same manner as in the state where the temperature rise, the power supply voltage fall and the transistor characteristics are slowed. In this state, the driving capability of the buffer 33 is improved, and the delay of the delay time due to the wiring capacitance and the input capacitance of the flip-flops 31 and 32 at the next stage can be reduced. As a result, the value of the delay difference T ₂ due to the wiring length L ₂ shown in FIG. 8 being sufficiently longer than L ₃ is also reduced. Further, assuming that the drive capability variable circuit inserted in the signal path of the flip-flop 31 is set in the same manner as the above-described state where the temperature drop, the power supply voltage rise and the transistor characteristic become fast, in this state, the flip-flop 31 The driving capability of the circuit is decreased, and the delay T _{4 of the} delay time due to the wiring capacity and the input capacity of the flip-flop 32 at the next stage can be increased.

That is, as is clear from the above, the driving capability of the buffer 33 is increased, the delay time of the signal input to the C terminal of the flip-flop 32 is shortened, and the D terminal of the flip-flop 32 is connected. By delaying the delay time of the input signal, the flip-flop 32
The result that meets the conditions regarding the hold time is obtained, and the stable operation of the circuit is guaranteed.

[0022]

As described above, according to the present invention, the CMO
By providing a predetermined drive capacity variable circuit and a memory for controlling the drive capacity variable circuit in the S integrated circuit, the CM can be controlled via the level state of the memory set from the outside.
It is possible to control the variation in the delay time in the OS integrated circuit, and it is possible to facilitate the circuit design and to operate the CMOS integrated circuit in a stable manner.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal configuration of a drive capacity variable circuit and a buffer in this embodiment.

FIG. 3 is a circuit diagram showing a conventional example.

FIG. 4 is a timing chart showing an operation in the conventional example.

FIG. 5 is a circuit diagram showing another conventional example.

FIG. 6 is a timing chart showing an operation in the conventional example.

FIG. 7 is a circuit diagram showing another conventional example.

FIG. 8 is a timing chart showing an operation in the conventional example.

[Explanation of symbols]

1 CMOS integrated circuit 2, 4, 24, 25, 27, 29, 31, 32 Flip-flop 3, 6 Driving capacity variable circuit 5, 26, 30, 33 Buffer 7 Memory 8, 11, 14, 19 Inverter 9, 12, 15, 16, 20, 21 P channel MO
S-transistors 10, 13, 17, 18, 22, 23 N-channel M
OS transistor 28 delay circuit

Claims (2)

[Claims] 1. A CMOS integrated circuit having predetermined functional blocks, which is rewritable from the outside and stores a predetermined control set value input from the outside, said control memory; A driving capacity variable circuit that is inserted and connected to a signal path including a functional block and that receives a control setting value output from the control memory and controls and adjusts the driving capacity of the functional block. CMOS integrated circuit. 2. A first P-channel MOS transistor, wherein the variable drive capacity circuit has at least a source connected to a high-potential-side power supply and a gate connected to a first output terminal of the control memory, A source is connected to the drain of the first P-channel MOS transistor, an inverted signal of a predetermined input signal is input to the gate, a reinverted signal of the inverted signal is input to the drain, and an output terminal is connected. A second P-channel MOS transistor having a drain connected to the drain of the second P-channel MOS transistor and a gate connected to the second P-channel M transistor.
A first N-channel MOS transistor connected to the gate of the OS transistor, a first inverter whose input end is connected to the first output terminal of the control memory, and a drain whose first N-channel MOS transistor is connected. A second N-channel MOS transistor connected to the source of the transistor, the gate of which is connected to the output terminal of the first inverter, the source of which is connected to the power source on the low potential side, and the source of which is connected to the power source on the high potential side. A third P-channel MOS transistor connected to the control memory and having a gate connected to the second output terminal of the control memory; a source connected to the drain of the third P-channel MOS transistor; Of the fourth P-channel to which the reversal signal of the reversal signal is input to the drain and the output terminal is connected. And a drain connected to the drain of the fourth P-channel MOS transistor and a gate connected to the fourth P-channel M
A third N-channel MOS transistor connected to the gate of the OS transistor, a second inverter having an input end connected to the second output terminal of the control memory, and a drain having the third N-channel MOS transistor A fourth N-channel MOS transistor connected to the source of the transistor, connected at the gate to the output terminal of the second inverter, and connected at the source to the low-potential-side power supply. 1. The CMOS integrated circuit according to 1.