JPH0434954A - Standard-cell type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the integration density of an integrated circuit and to stabilize electric characteristics such as an operation speed by providing a cell comprising a transfer gate and a capacitor element. CONSTITUTION:One electrode of a MOS capacitor element is connected to a nodal point 2 at a second Al wiring layer in order to prevent erroneous operation due to charge share. MOS capacitor elements CA and CB have a structure wherein the source and the drain of an N-channel MOS transistor of a silicon gate are shorted. In this example, the electrode is connected to the output side of the transfer gate. The electrode can be connected to the input side depending on the constitution of the circuit. Since the MOS capacitor element is arranged in the same region as a transfer gate cell, the same area as that of a conventional transfer gate cell can be provided. Since the connection is provided at the necessary places at the second Al wiring layer, the charge share can be corrected in a short period. Since the wiring distance is short in this way, undesirable interaction can be made less. Thus, the integrated circuit whose characteristics are stable can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a standard cell type semiconductor integrated circuit, and more particularly to a standard cell type semiconductor integrated circuit having a transfer gate.

[Conventional technology]

In a standard cell type semiconductor integrated circuit having a transfer gate, malfunction due to charge sharing may be discovered when the transfer gate cell is used in the semiconductor chip stage. This malfunction can be avoided by adding a capacitor and increasing the load capacitance of the transfer gate, but this requires remanufacturing the semiconductor chip from the initial manufacturing process.

FIG. 2 shows an example of a circuit that may cause malfunction due to charge sharing.

There is a transfer gate between the output end of inverter 1 and node 2.
) TR12, transfer between nodes 2 and 3 -) TR
23, node 2 has a capacitance C2°, and node 3 has a capacitance C3.

Here, the capacitances C2 and C3 may be stray capacitances. FIG. 3 shows a timing chart of the operation of the circuit shown in FIG. In FIG. 3, during the period t1, the output of the inverter 1 is HIGH, the control signal 4 is HIGH, and the control signal 5 is LOW.
) TR23 is in the OFF state, and when the potential of the node 2 is set to V, the capacitor C2 is charged with a charge of C2·■. Also, capacitor 3 has already been discharged and the potential at node 3 is O [■]
shall be.

Next, in the period t2, since the node 4 is LOW and the node 5 is HIGH, the transfer gate TR12 is in the OFF state and the transfer gate TR23 is in the ON state, and the period t1
A part of the charge C2・V charged in the capacitance C
Charge sharing occurs, such as moving to charge 3. At this time, if the potential of node 3 is v3, then C2・V= (C2+C3)−V3 ・−・−
(1) holds true. Therefore, ■3 is given by. This potential v3 is the HI of inverter 6.
There is no problem as long as it is higher than the threshold value that can be considered as GH. However, if C2<C3 (3), then the potential v3 at node 3 may be lower than the threshold value for inverter 6 to be considered HIGH, as shown by the broken line in FIG. This will cause a malfunction. Therefore, if a malfunction occurs due to charge sharing, node 2
It is necessary to increase the capacitance between the node 3 and the ground terminal, and raise the potential of the node 3 to a threshold value that can be considered as the HIGH of the inverter 6 during the period t2.

Conventionally, in semiconductor chips whose layout was designed using the stand-start cell method, if a malfunction occurs due to charge sharing and the layout must be corrected,
Either a new capacitor had to be added, or an unused capacitor or gate had to be found and a metal wire had to be extended and connected to that location. In the former case, as shown in FIG. 4, an inverter cell.

Since it is necessary to add the capacitor C at a location different from the transfer gate cell, the process of manufacturing the semiconductor chip must be restarted from the beginning, and the period of the manufacturing process is also long. This method requires a capacitor in addition to the standard cell, which leads to a deterioration in the degree of integration, and since the wiring passes over other cells, it may cause new malfunctions.

In the latter case, it cannot be corrected if there is no unused capacitor or gate serving as a load capacitance. Furthermore, even if these exist, it is difficult in many cases to connect them to a point where the capacitance is to be increased using metal wiring.

Although it is possible to avoid malfunctions by preparing a cell with a capacitive element connected in advance to the input or output side of the transfer gate where charge sharing is likely to occur, it is possible to prevent malfunctions due to charge sharing when designing the layout. Since it is difficult to predict the actual value of the capacitive element, the risk of connecting an unnecessary capacitive element cannot be avoided, and a decrease in operating speed is inevitable.

[Problem to be solved by the invention]

As mentioned above, in conventional standard cell type semiconductor integrated circuits, standard cells do not include capacitive elements, so those created according to the layout design may malfunction due to charge sharing in the transfer gate cell section. In this case, the layout must be modified.

To do this, you must either add a new capacitor C as shown in Figure 4, or find an unused gate or capacitor and connect it to the point where you want to add capacitance with metal wiring. In the former case, the manufacturing process must be performed from the beginning, and it takes a long time to complete the semiconductor chip after layout correction. In the latter case, there must be unused capacitors or gates that can become capacitors on the wafer that has gone through the process before metal wiring, and these and the places where you want to add capacitance with metal wiring must be connected with new metal. Additional wiring must be found and connected, which is not always possible. Furthermore, in both cases there is a risk of undesired interaction with other parts of the circuit through the metal wiring. Furthermore, connecting a capacitor to the input side or the input side of the transfer gate during layout design increases current consumption, resulting in a decrease in operating speed.

In any case, in the conventional technology, the turnaround time (T
Even if the electrical characteristics such as the length of AT) or the electrical characteristics such as the degree of integration or operation speed are sacrificed, some drawbacks cannot be avoided.

[Means to solve the problem]

A standard cell type semiconductor integrated circuit according to the present invention has a cell consisting of a transfer gate and a capacitive element.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan layout diagram showing an embodiment of the present invention.

In this embodiment, the circuit shown in FIG. 2 is implemented using a standard cell system. In the figure, the marbled areas with many dots are the polycrystalline silicon film, and the roughly shaded areas are the 1st wiring layer 2. The densely shaded areas are the 2nd wiring layer 2.
It is one wiring layer. The difference from the conventional example is that MO8 capacitive elements CA and CB are arranged in the same area as the transfer gate cell. In the figure, one electrode of the MO8 capacitive element is connected to the second A to prevent malfunction due to charge sharing.
It is connected to node 2 on the A wiring layer. MO8 capacitive element CA
, CB have a structure in which the source and drain of a silicon gate N-channel MOS transistor are short-circuited. In this embodiment, it is connected to the pressure side of the transfer gate, but it may be connected to the input side depending on the circuit configuration.

Since the MO8 capacitive element is arranged in the same area as the transfer gate cell, the area can be the same as that of the conventional transfer gate cell.

Since the second Aρ wiring layer can be used to connect the required locations, the charge share can be corrected in a short period of time.

Further, since the wiring distance for this purpose can be shortened, undesirable interactions can be reduced.

〔Effect of the invention〕

As explained above, since the present invention has a cell consisting of a transfer gate and a capacitive element, the drain or source of the transfer gate and the capacitive element can be easily connected with metal wiring as needed. If you have a wafer from the previous process, you can obtain a semiconductor chip in which the capacitor and the drain or source of the transfer gate are connected in a short period of time.

Therefore, if malfunctions due to charge sharing in the transfer gate section are discovered at the semiconductor chip stage after layout design, it is possible to correct the metal wiring layout and redo the metal wiring process to create a semiconductor chip that will not malfunction due to charge sharing. It has the effect of being easily obtainable in a short period of time.

Furthermore, since the capacitive element is placed near the transfer gate, correction can be performed reliably, and an integrated circuit with stable characteristics can be provided.

11... Contact between diffusion layer and second A7 wiring layer, 12... Contact between polycrystalline silicon film and second AJ2 wiring layer, I3... P-type diffusion layer, 14...
・Mark・Nff diffusion layer, 15.17... N-type diffusion layer of MO8 capacitive element, 16.18... Electrode of MO8 capacitive element, C1CA, CB... Capacitive element, C2, C3...
····capacity.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

FIG. 1 is a plan layout diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a circuit that causes charge sharing, FIG. 3 is a timing chart of the operation of the circuit in FIG. 2, and FIG.
The figure is a plan layout diagram showing a conventional example. l... Inverter, 2, 3... Node,
4.4N. 4P, 5.5N, 5P... Control signal line, 6...
...Inverter, 8...Power supply wiring, 9...
...Ground wiring, 10...Diffusion layer - 1st Aj
7 Contacts between wiring layers, Shimoseki Seizu Party Diagram

Claims (1)

[Claims] A standard cell type semiconductor integrated circuit characterized by having a cell consisting of a transfer gate and a capacitive element.