JPH0435103A - Digital signal complexization method, realization method and device - Google Patents

Abstract

PURPOSE:To slow down the speed of a multiplier for filtering by using a sign inverter, plural sub filters resulting from decomposing one digital filter and an adder only for the acquisition of a complex number signal from a real part signal. CONSTITUTION:Filter operation is applies to a signal by using sub filters 110, 113, 112, 111 whose transfer functions are respectively H0(-Z<4>), H3(-Z<4>), H2(-Z<4>), H1(-Z<4>), and outputs of the sub filters 111, 112, 113 are delayed by a delay section 103, a sum section 120 adds the sub filters 110, 112 as a real part output and a sum section 121 adds the sub filters 111, 113 as an imaginary part output, and the delay section 103 is used in common for a sign inversion section 101 and a sign inversion section 151 extracts four inputs each and sign inversion and non-inversion are repeated.

Description

[Detailed Description of the Invention] Industrial Application Fields of the Invention 11 Frequency conversion of digital signals when digital signal processing is performed on signals modulated in the RF band, etc. Complex conversion including filtering Realization method and device It is related to.

Conventional technology Conventionally, as shown in Figure 3(a), f/2 to 3f/2
In order to obtain a complex signal 304 by frequency converting a signal 301 having a band f in a frequency range of -f/2-f/2 as shown in FIG. 3(e), Figure 3 (
It is digitized at a sampling frequency of 4f as shown in b), and then frequency-shifted as shown in FIG. 3(C) by multiplying by a complex number exp (-jnπ/2).

(Here, n I & indicates the number of the input digital signal sequence.) Furthermore, by using a filter with characteristic 303, only the frequency range from -f/2 to f/2 is filtered as shown in Fig. 3(d). Take it out. By decimating this by 1/4, the result is as shown in Figure 3(e). Q complex signal 3
Conversely, as shown in Figure 3(e), a complex signal 304 with a band of f in the frequency range of -f/2 to f/2 is obtained as shown in Figure 3(b). f/2~3f
In order to obtain the real signal 302 by converting the frequency to the frequency range of /2, the complex signal 304 is converted into the frequency range (2 -f/ Extract only the frequency range from 2 to f/2. Next, by multiplying by the complex number exp (-jnπ/2), shift the frequency to (to) as shown in Figure 3 (b'). Extract only the real part of this data. As a result, as shown in FIG. 3(b), a real signal 302 is obtained in the frequency range of f/2 to 3f/2.The problem to be solved by the invention is the complex signal including frequency conversion and filtering of digital signals. If we do this using the above method, we get the complex number eXp(-j
n yr /2) multiplication unit 401, filtering calculation unit 40 for extracting the frequency range of -f/2-f/2
2, 403, decimation sections 404, 405 or interboration sections 406, 407, respectively.
An object of the present invention is to provide a method and apparatus for solving the problem described in item 1 above.

Means for Solving the Problems The present invention has been made to solve the following problems, and is a method for obtaining a complex signal from a real signal.After selectively inverting the sign of a digital signal sequence, This is input to multiple sub-filters that are decomposed from one digital filter, and the outputs of these sub-filters are combined (added) to obtain a complex signal.

In addition, in order to obtain a real signal from a complex signal, the sign of a digital signal sequence in a complex signal format is selectively inverted, and then this is sent to multiple subfilters that are decomposed from one digital filter.Input - Output of this subfilter A real signal is obtained by sequentially outputting the following signals.

The present invention (as described above) is a filtering operation for extracting the frequency range from f/2 to f/2 multiplied by the complex number exp (-jnπ/2). The decimation, which required a three-stage digital signal processing means, now requires only a plurality of filters and an adder, which are obtained by decomposing one digital filter.

To obtain a real signal from a complex signal, multiply the complex number eXI) (-j n yr /2)! , -f/2
- The demonstration of filtering to extract the f/2 frequency range required a three-stage digital signal processing means for interpolation (multiple subfilters decomposed from one digital filter and Only the selector is required.As shown below, the amount of hardware can be reduced.

Furthermore, the difference between the conventional filter for extracting the frequency range from 1 f/2 to f/2 and the FIR filter is that the plurality of sub-filters are decomposed versions of the FIR filter, and essentially perform one filtering process. , multiple sub-filters are processing in parallel. Therefore, the speed of the multiplier for filtering can be slowed down, making implementation easier.

Embodiment FIGS. 1(a) and 1(b)i are block diagrams of a complexization device in an embodiment of the present invention.

The digital input signal X (n) sampled at 4f as shown at 302 in Fig. 3(b) is Z-transformed, and the input order is divided into 4 signals as shown in the following equation, X(Z)-L. (Z')+Z-'X+(Z')+Z-2L
(Z') + Z-3Xs (Z') This is complex number exp (
-jnπ/2). This (yo) In the above formula,
There is no choice but to replace 2 with -jZ. Therefore,
By this multiplication, X(Z)clX(-jZ)=Xe(Z
')+jZ-'X+(Z')Z-2X2(Z')+jZ
The frequency is converted to -3X3(Z'). The transfer function of the filter with the characteristic 303 shown in FIG. 3(C) is Z-transformed and H(Z
), the tap coefficients of the filter are decomposed and grouped into four coefficients as shown in the intermediary formula.

H(Z)=Ha(Z')+Z-'H+(Z'
)+Z-2H2(Z')+Z-" Ha (Z') Therefore, to obtain 304 in Figure 3(e), H(Z)・X
Calculate (-jZ) and further 1/4 decimation L
If Az is replaced with Zexp(-jπ/4) and the formula is rearranged, the output will be as shown in the following formula.

Hll(-Z')・Xl! (-Z')+Z-'H1!
(-Z')42(-Z')+jZ-' ((Hs(
-Z')4+(-Z')-H+(-Z')4a(-Z'
))) As shown in Fig. 1(a), the sign inverter 101 extracts the input every 4 bits and inverts the sign (repeat the sign inversion and non-inversion every 4 bits) L sequentially, transfer function power <, Hs(-Z'), Hs(-Z'), H
2 (-Z'), H+ (-Z') The filter operation is performed by the tail subfilter 1113, 112, 111 (＼ The output of the subfilter 111, 112, 113 is delayed by the delay unit 103, and the output of the subfilter 111, 112, 113 is delayed by the delay unit 103, 120, 12
1 means that the output is obtained with the addition outputs of the sub-filters 110 and 112 as the real part and the addition outputs of the sub-filters 111 and 113 as the imaginary part. Further, in FIG. 1(a), the delay section 103 is replaced by the sign inverting section 10.
1, as shown in FIG. 1(b), the sign inverter 151 extracts the input every 4 digits and repeats sign inversion (sign inversion and non-inversion every 4 digits.However, only the input of the sub-filter 160) It is in reverse phase with the others.)L sequentially,
Transfer function f) < Ih (-7'), H2(-Z'
), -H+ (-Z'), H@(-Z'), sub-filters 163, 162, 161.160 perform filter calculations, l, X, adders 170, 171,
The output can be obtained by using the added outputs of the sub-filters 160 and 162 as the real part and the added outputs of the sub-filters 161 and 163 as the imaginary part.

Comparing Fig. 1(b) and Fig. 3(a), the complex multiplier, two filters, and two decimation sections are required (only the sign inversion section, subfilter starvation, and addition section are required, and the amount of calculation is It can be seen that there has been a considerable decrease.

FIG. 2 is a block diagram of a realization device in a second embodiment of the present invention.

Figure 3(e) 304f Complex signal X(Z')=Xr(Z')+X1(Z')? It is obtained by multiplying the Q complex number exp (-jnπ/4).

That is, in the above formula, 2 is replaced with Zexp(-jπ/4). Therefore, X(-Z')=Xr(-Z')+jXi(-Z').

Transfer function H of the filter with characteristic 305 shown in FIG. 3(e)
Set (Z) as the following formula, H(Z)=)l@(Z')+Z-'H+(Z')+Z-
2Ha(Z')+Z-'Hs(Z')Figure 3(b) 30
2 is obtained by calculating H(z)·x(-jz) and further multiplying by the complex number eXp(-jnπ/2).

If we replace z with -jz, extract only the real part, and rearrange the formula, we get the output (the following formula).

He(Z')4r(-Z') -Z-' H+ (
Z')4i(-2')Z-2H2(Z')4r(-
Z')+Z-'H3(Z')・Xl(-Z')This c main As shown in FIG.
The real part and the imaginary part of the complex input are sequentially sign-inverted (sign-inverted and non-inverted are repeated for each input) L, soh transfer function h<T(ll(Z') and -H2(Z'),
H+ (Z') and Ha (Z') are input to certain subfilters 21o and 212, 211 and 213, and filter calculations are performed ((subfilters 210, 2
This means that the outputs should be taken out in order from 11°, 212, and 213.

Comparing Fig. 2 and Fig. 3 (b), two interpolation sections, two filters, and a complex multiplication section are required, but only a sign inversion section, a subfilter pulse, a selector section are required, and the calculation It can be seen that the amount has decreased considerably.

Effects of the Invention As described above, according to the present invention, in order to obtain a complex signal from a real signal, only a plurality of filters and an adder are required. In order to obtain a real signal from a signal (sign inversion), only multiple filters and selectors are required, which are obtained by decomposing a single digital filter.As described above, the amount of hardware can be reduced.

Also, if the filter is an F-R filter ('L), one filtering process is actually processed in parallel by multiple sub-filters, and the speed of the multiplier for filtering is slowed down. It is easy to realize, and its practical effect is very good.

[Brief explanation of the drawing]

Figure 1 (a) (b) l;L Figure 2 shows the blocks of the complexizer in one embodiment of the present invention; Figure 2 shows the blocks of the realizer in the second embodiment of the invention; Figure 3 shows the conventional 4A and 4B are block diagrams of a conventional complexization method and a realization device, respectively. 101, 151, 201... sign inversion S, ZO111
1, 112, 113, 160, 161, 162, 163
, 210, 211, 212, 213... Subfill Ku 103... Delay copying 120, 121, 170, 17
1...Addition unit, 303, 305...Filter characteristics, 401...Complex multiplication starvation 402.403...Fill length 404, 405...Decimation = 6 4
06, 407--・Interboration accent Agent's name Patent attorney Shigetaka Awano

Claims (4)

[Claims] (1) means for selectively inverting the sign of a digital signal sequence in a real signal format; means for inputting the output of the sign inverting means to a plurality of sub-filters obtained by decomposing one digital filter; and the output of the sub-filters. What is claimed is: 1. A digital signal complexization device comprising means for combining and adding. (2) means for selectively inverting the sign of a digital signal sequence in a complex signal format; means for inputting the output of the sign inverting means to a plurality of subfilters obtained by decomposing one digital filter; and an output of the subfilter. What is claimed is: 1. A digital signal realization device, characterized in that it is provided with means for sequentially outputting. (3) Selectively sign-inverting a digital signal sequence in a real signal format, inputting the sign-inverted signal to a digital filter consisting of a plurality of sub-filters, and combining and adding the outputs of the sub-filters. A method for complexizing digital signals. (4) A digital device characterized by selectively inverting the sign of a digital signal sequence in a complex signal format, inputting the sign-inverted signal to a digital filter consisting of a plurality of sub-filters, and sequentially outputting the outputs of the sub-filters. How to make signals real.