JPH0435367A - Synchronous separation device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization separation device that separates a synchronization signal of a video signal into a digital signal.

BACKGROUND OF THE INVENTION In recent years, as the digitalization of video signals has progressed, various types of synchronous separation circuits have been considered.

An example of the above-mentioned conventional synchronization separation device will be described below with reference to the drawings.

FIG. 7 shows a block diagram of a conventional synchronization separation device. 7th
In the figure, 1 is a clamp circuit, 2 is an A/D converter, and 3
4 is an LPF, 4 is a synchronization separation circuit, and 5 is a minimum value detection circuit that detects the minimum value of the LPF 3 and controls the synchronization/separation circuit 4. Here, the A/Dt converter 2 is configured, for example, as a parallel comparison type as shown in FIG.

The operation of the synchronization separation device configured as described above will be described below. First, the input video signal is clamped at the back porch in clamp circuit 1, and A
/D conversion 2, the signal is converted into a digital signal. Next, the LPF 3 limits the band and removes noise. Then, the minimum value detection circuit 5 detects the minimum value of the synchronization signal part b) as shown in level A in FIG. 6, and the synchronization separation circuit 4 detects the minimum value (level A) and the back porch level (level C) intermediate level (level B
), synchronization separation is performed and a synchronization signal (cl) is output.

Problems to be Solved by the InventionHowever, in the above configuration, when the synchronization signal portion of the input video signal is smaller than the standard signal, for example,
Input synchronization signal part molecule al input to A/D & converter 2
Assuming that FIG. 3 is the standard signal, FIG. 4 shows the input synchronizing signal portion (at or approximately 1/2).

However, Ref H, Ref C, and Ref L are reference voltages corresponding to the maximum level, back porch level, and minimum level of the A/D converter 2, as shown in FIG. When a signal like that shown in Fig. 4 is input, the resolution is reduced to 1/2 because the synchronization signal is 1/2 as small. In other words, A
If the /D converter 2 is nbit, the synchronization signal is approximately 1/4 of the entire video signal when it is a standard signal, so it is equivalently (n
-2) bit, but when the synchronization signal becomes 1/2 (n
-3) bit, resulting in a significant deterioration of synchronization performance.

The present invention solves the above-mentioned problem, and aims to provide a synchronization separation device that does not deteriorate synchronization performance even if the synchronization signal portion becomes small.

Means for Solving the Problems In order to solve the above problems, the synchronization separation device of the present invention uses a D/A that converts the minimum value (synchronization signal part) into an analog signal.
A converter is provided, and the low level of the reference voltage of the A/D converter is controlled based on the output of the converter.

Operation With the above-described configuration, even when the synchronization signal portion of the input signal is small, the low level of the reference voltage of the A/D converter can be controlled and the resolution can be kept constant.

Embodiment Hereinafter, a synchronization separation device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a synchronization separation device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a parallel comparison type A/D f converter. In Fig. 1, 1 is a clamp circuit, 2 is a parallel comparison type A/D converter, 3 is an LPF, 4 is a synchronous separation circuit, and 5 is a minimum value detection circuit, which is similar to the conventional example. Has a function. 6 is a D/A converter which converts the minimum value obtained by the minimum value detection circuit 5 into an analog signal, and controls the reference voltage of the A/Df converter 2 with its output.

In Figure 2, 7 is a voltage dividing resistor that divides the reference voltage;
9 is a comparator that compares the divided voltage and the clamp output; 9 is a latch circuit that latches the output of the comparator 8; and 10 is an encoder that encodes the output of the latch circuit 9.

The operation of the synchronization separation device configured as described above will be described below with reference to the drawings. First, the input video signal is clamped in the clamp circuit 1 so that the back porch level becomes the reference voltage RefC of the A/D converter 2. When the video signal is a standard signal, the synchronization signal part is approximately 174, so for example, nbit A/D
When using an f resistor, 2n resistors 7 and (2°-1) comparators 8 are required, or RefC is 2n from RefL.
It is assumed that the voltage is between the n-2nd and 2n''+1th resistors.

Then, it is converted into a digital signal by the A/D f converter 2,
Bandwidth is limited by LPF3 and noise components are removed. Next, the minimum value is detected in the minimum value detection circuit 5, and using that value, the synchronization signal portion (bl) is subjected to synchronization separation in the synchronization separation circuit 4, and is output as a synchronization signal (cl).

Further, the minimum value obtained from the minimum value detection circuit 5 is converted into an analog signal in the D/A converter 6, and the reference voltage RefL of the A/Df converter 2 is controlled by its output. In other words, the minimum value found by the minimum value detection circuit 5 is the fifth
As shown in the figure, by controlling the reference voltage Ref L in the direction of fixing it to a certain digital value, the resolution of the synchronizing signal portion can be made constant.

Effects of the Invention As described above, according to the present invention, a D/A converter that converts the minimum value into an analog signal is provided, and the low level of the reference voltage of the A/D converter is controlled by the output of the D/A converter, thereby achieving synchronization. Even if the signal becomes smaller, the resolution can be kept constant and synchronization separation can be performed without deteriorating synchronization performance.

[Brief explanation of the drawing]

FIG. 1 shows the synchronous portion 1lIII in one embodiment of the present invention.
2 is a block diagram of the A/D converter, FIGS. 3 to 6 are waveform diagrams for explaining the operation of the synchronous separator, and FIG. 7 is a conventional synchronous separator. FIG. 1... Clamp circuit, 2... A/D converter, 3...
・LPF. 4... Period separation circuit, 5... Minimum value detection circuit, 6...
・D/A converter, 7... Resistor, 8... Comparator, 9.
...Latch circuit, 10-...Encoder, Ref H,
Ref C, Ref L-Reference voltage.

Claims (1)

[Claims] 1. A clamp circuit that clamps the video signal, an A/D converter that converts the output of the clamp circuit into a digital signal, an LPF that limits the band of the A/D converter, and a minimum value from the output of the LPF. a minimum value detection circuit that detects
a synchronization separation circuit that performs synchronization separation of a synchronization signal from the output of the LPF using the output of the minimum value detection circuit; and a synchronization separation circuit that converts the output of the minimum value detection circuit into an analog signal, A synchronous separation device equipped with a D/A converter that controls the low level.