JPH0435471A - High definition receiver - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention provides an analog MUSE signal and a digital MUSE signal.
This paper focuses on a high-definition receiver capable of receiving and processing signals, and particularly focuses on its synchronization circuit.

(Conventional example) MUSE (multi
plesub-Nyquist sawpuling
encoding method has been developed. This method is disclosed in Japanese Patent Application Laid-Open No. 61-284889, Nikkei Electronics 19B7.11.2 P189-P211.

In the MUSE method, a sampling clock is not transmitted from the encoder side, and the decoder reproduces the clock using a synchronization signal.

FIG. 8 shows a frame format of a signal in the MUSE system. In the figure, the area labeled VITS is the area to which the particle interval test signal is allocated, the area labeled C video is the area to which the compressed color signal is allocated, and the area labeled Y video is the area to which the compressed color signal is allocated. This is an area to which video signals are allocated. Also H
The area marked D is an area to which a horizontal synchronization signal is allocated.

The HD signal is inserted for each line as shown in FIG. 9, and the decoder side reproduces the sampling clock based on this signal. This circuit is called a synchronous regeneration circuit.

FIG. 7 shows a conventional synchronous reproducing circuit.

An analog MUSE signal is supplied to an input terminal 1 and is digitized by an analog-to-digital (A/D) converter 2 . The digitized MUSE signal is input to the phase error detection circuit 3, where the phase error of the horizontal synchronization signal is detected. For the horizontal synchronization signal, a phase detection point (HD point) is determined in advance as shown in FIG. Therefore, if the sampling signal obtained at this HD point does not have a predetermined value, it means that the sampling pulse is out of phase, and the error output is passed through the filter 4 to the digital-to-analog (D/A) converter 5. is input.

The output of the digital-to-analog converter 5 is supplied to a control terminal of a voltage-controlled oscillator 6 using a crystal. The oscillation output of the voltage controlled oscillator 6 is used as a sampling clock and as a pulse for creating an internal frame pulse. That is, it is supplied to the horizontal counter 8. This horizontal counter 8 obtains the horizontal address of each line, and its line count output is also supplied to the vertical counter 9. The vertical counter 9 obtains a vertical address and generates an internal frame pulse corresponding to a VITS frame pulse (hereinafter referred to as an external frame pulse).

The internal frame pulse is input to the window width setting circuit 10. This window width setting circuit 10 is a circuit that sets the pulse width of the internal frame pulse to be slightly wider than the pulse width of the external frame pulse. The internal frame pulse output from the window width setting circuit 10 is input to one input terminal of the out-of-synchronization detection circuit 11. On the other hand, the output of the analog-to-digital converter 2 is input to a frame pulse detection circuit 7, where an external frame pulse is detected.

This external frame pulse is supplied to the other input terminal of the out-of-sync detection circuit 11.

The out-of-synchronization detection circuit 11 detects whether or not the pulse of the external frame pulse exists within the pulse width of the internal frame pulse, and if it exists, it is in a synchronized state, and if it does not exist, it outputs a detection signal as an out-of-synchronization state. obtain. In the out-of-synchronization state, the filter 4, horizontal counter 8, and vertical counter 9 are reset by the detection signal and set to the initial state. This will start synchronization pull-in from the beginning.

(Problems to be Solved by the Invention) Recently, with the advancement of digital technology, there is a possibility that a receiver having a digital input section will appear even in high-definition receivers. In other words, a system may be considered in which the conventional digital MUSE signal from the encoder side is directly introduced into the decoder side.

For such a system, analog-to-digital converter 2
Signal processing can be performed without passing through.

FIG. 6 is an example of a synchronous regeneration circuit that can be considered when considering a MUSE type receiver equipped with a digital input section.

In addition to the configuration shown in FIG. 7, a digital input section 12, switches 13 and 16, a phase error detection circuit 14, and a filter 15 are added. A digital MUSE signal is supplied to a terminal M of the digital input section 12, and a clock is supplied to a terminal CK. The clock is supplied to a phase error detection circuit 14. The phase error detection circuit 14 detects the phase error of the clock and supplies it to the filter 15. The output of filter 15 is supplied to one input terminal of switch 16.

This switch 16 is switched to select the output from the digital-to-analog converter 5 when receiving the analog MUSE signal, and to select the output from the filter 15 when receiving the digital MUSE signal. The output of switch 16 is provided to a voltage controlled oscillator 60 control terminal. The output of the voltage controlled oscillator 6 is used as a sampling clock.

When detecting the phase error of the sampling clock, the (D signal) is used when the analog MUSE signal is being processed, and the clock is used when the digital MUSE signal is being processed. This is because when processing the digital MUSE signal, the acquisition speed can be obtained faster by using the HD pulse or by directly using the clock.Therefore, in this case, the phase error detection circuit 14, filter 15, A switch 16 is required.

Further, the switch 13 selects the output of the analog-to-digital converter 2 when the analog MUSE signal is processed, and selects the output of the analog-to-digital converter 2 when the analog MUSE signal is processed, and selects the input terminal M when the digital MUSE signal is processed.
Select. The selected output is then supplied to the frame pulse detection circuit 7.

According to the above-mentioned synchronous reproducing circuit, since the clock is used as a synchronization reference, synchronization can be quickly acquired when processing a digital MUSE signal, and the circuit has the advantage of being resistant to input signal jitter.

However, if the clock is momentarily lost in a synchronized state, or if noise jumps into the control voltage of the voltage controlled oscillator, the clock synchronization will be instantaneously lost.

However, even if the clocks are out of synchronization, this system cannot detect the out-of-synchronization condition because the pulse width of the internal frame pulse is slightly wider than the external frame pulse. That is, for example, when the clock synchronization is momentarily lost, the internal frame pulse becomes the external frame pulse (digital MUS
Even if there is a deviation of ±1 clock from the predetermined phase relationship of the E signal), no out-of-synchronization is detected. In such a case, even if the clocks are brought out of synchronization, the internal frame pulse and the external frame pulse will remain out of phase with each other, making it impossible to detect out-of-synchronization. When processing analog MUSE signals, in the case of HD signals, H
There is no problem because the clock is pulled to the D point, but when clock synchronization is to be obtained, the synchronization state will be achieved even if the clock is deviated by one cycle.

Moreover, at this time, if there is a phase shift between the internal frame pulse and the external frame pulse, video processing will not be performed at the correct timing, leading to problems such as a shift between the color signal phase and the luminance signal phase. Ru.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-definition receiver that can reliably detect out-of-synchronization even during digital MUSE signal processing.

[Structure of the Invention] (Means for Solving the Problems) (1) The present invention provides an analog-to-digital conversion means for digitizing an analog MUSE signal, which is a high-definition transmission system, and outputting it as a first MUSE signal; In the synchronization regeneration circuit of the receiver, which has a digital MUSE signal input section that is supplied as a signal or a second MUSE signal, and can synchronize with either MUSE signal, the external frame pulse contained in the external signal and , when detecting synchronization by comparing the internal frame pulse with an internally generated internal frame pulse, a means for generating the internal frame pulse with a narrower pulse width than that during the first MUSE signal processing is used when processing the second MUSE signal. It is something to be prepared for.

(Function) The above means increases the accuracy of the out-of-sync detection function during digital MUSE signal processing, and contributes to always obtaining normal reproduced images.

(2) Furthermore, the present invention digitizes the analog MUSE signal, which is a high-definition transmission system, and transmits the first MUSE signal.
It has an analog-to-digital conversion means that outputs it as an E signal, and a digital MUSE signal input section to which the digital MUSE signal is supplied as a second MUSE signal.
In the synchronization regeneration circuit of the receiver that can also be synchronized with the SE signal, when processing the second MUSE signal, the means for resetting the frame pulse generator is configured to synchronize with the output of the out-of-synchronization detection means and the second MUSE signal.
The reset pulse is generated using the horizontal synchronizing pulse of the MUSE signal itself.

(Function) With the above means, the synchronization pull-in operation during digital MUSE signal processing is pulled into accurate phase, which can contribute to always obtaining normal reproduced images.

(3) Furthermore, the present invention digitizes the analog MUSE signal, which is a high-definition transmission system, and transmits it to the first MUS.
It has an analog-to-digital conversion means that outputs it as an E signal, and a digital MUSE signal input section to which the digital MUSE signal is supplied as a second MUSE signal.
In the synchronization regeneration circuit of the receiver, which can also be synchronized with the SE signal, when processing the second MUSE signal, there is a means for controlling the internal oscillation means by comparing the phases of the external clock and the internal clock, and a means for stabilizing the internal oscillation means. and means for controlling the internal oscillation means by comparing the phases of the horizontal synchronizing pulse and the internal horizontal synchronizing pulse.

(Function) With the above means, during digital MUSE signal processing,
Since it is a clock phase comparison, high-speed acquisition is possible, and once a stable state is reached, the phase is controlled by horizontal synchronization pulses, which contributes to always obtaining normal image reproduction without being affected by jitter etc. .

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. The input terminal 31 has an analog MU including HD signals and external frame pulses.
The SE signal is provided and digitized by an analog-to-digital (A/D) converter 32. Digitized MU
The SE signal is input to a phase error detection circuit 33, where a phase error of the horizontal synchronization (HD) signal is detected. The horizontal synchronization signal is set in advance at the phase detection point (H
D point) has been arranged. Therefore, if the sampling signal obtained at this HD point does not have a predetermined value, it means that the sampling pulse is out of phase, and the error output is passed through the filter 34 to the digital-to-analog (D/A) converter 35. is input. The output of the digital-to-analog converter 35 is supplied to one terminal of the switch 51. This switch 51 selects the terminal 51A when processing the analog MUSE signal, and selects the terminal 51A when processing the analog MUSE signal.
When processing the USE signal, the other terminal 51D is selected. A switching signal for this selection is supplied from terminal 43. An error signal from the filter 45 is supplied to the terminal 51D.

A clock phase error output from the phase error detection circuit 44 is supplied to the filter 45 . Phase error detection circuit 4
4 detects the phase error of the clock supplied to the clock input terminal of the digital input section 42.

The output of the switch 51 is the voltage controlled oscillator 3 using a crystal.
6 control terminals. The oscillation output of the voltage controlled oscillator 36 is used as a sampling clock and as a pulse for creating an internal frame pulse. That is, it is supplied to the horizontal counter 38. This horizontal counter 38 obtains the horizontal address of each line, and its line count output is also supplied to a vertical counter 39. The vertical counter 39 obtains a vertical address and generates a VITS frame pulse, that is, an internal frame pulse corresponding to an external frame pulse.

The internal frame pulse is input to the window width setting circuit 40. This window width setting circuit 40 can set the pulse width of the internal frame pulse to be slightly wider than the pulse width of the external frame pulse, or can also set it to the same pulse width as the external frame pulse. This switching of the pulse width is controlled by a switching signal supplied from the terminal 43, and when processing the analog MUSE signal, the pulse width of the internal frame pulse is set slightly wider than the pulse width of the external frame pulse, and the pulse width of the digital MUSE signal is set to be slightly wider than that of the external frame pulse. When processing the internal frame pulse, set the pulse width of the internal frame pulse to the same pulse width as the external frame pulse.

The internal frame pulse output from the window width setting circuit 40 is input to one input terminal of the out-of-synchronization detection circuit 41.

Further, the output of the analog-to-digital converter 32 is supplied to one input terminal 52A of the switch 52. The other input terminal 52D of this switch 52 has a digital input section 4.
A digital MUSE signal from 2 is supplied. When processing the analog MUSE signal, this switch 52
When terminal 52A is selected and the digital MUSE signal is processed, control is performed by a switching signal from terminal 43 so that terminal 52D is selected.

The output of the switch 52 is input to a frame pulse detection circuit 37, where an external frame pulse is detected. This external frame pulse is transmitted to the out-of-sync detection circuit 4.
1 to the other input terminal.

The out-of-synchronization detection circuit 41 detects whether or not the pulse of the external frame pulse exists within the pulse width of the internal frame pulse, and if it exists, it is in a synchronized state, and if it does not exist continuously for a certain period of time, it is out of synchronization. Obtain a detection signal as the state. In the out-of-synchronization state, the filter 34, horizontal counter 38, and vertical counter 39 are reset by the detection signal and set to the initial state. This will start synchronization pull-in from the beginning.

FIG. 2 shows the window width setting circuit 40 and the out-of-sync detection circuit 4.
1 is specifically shown.

An output from the vertical counter 39 (vertical synchronization pulse) is supplied to the input terminal 401 . This pulse is supplied to the load terminal of 4-bit counter 402. counter 4
Data is supplied from the switch 403 to the data input terminal 02. The switch 403 is controlled by a switching signal from the terminal 43, and when the analog MUSE signal is processed, selects the data AD from the terminal A and selects the digital MUSE signal.
When the USE signal is processed, data DD from terminal p
is controlled to select and output.

The carry of the counter 402 is supplied to the enable terminal of this counter via an inverter 404, and is also input to the out-of-sync detection circuit 41 as an internal frame pulse. Therefore, when a vertical synchronization pulse is input, data is loaded into the counter 402, and a carry is obtained as the clock count progresses. Here, the data AD is set to a value that provides a carry when three clocks are counted, and the data DD is set to a value that provides a carry when one clock is counted. In other words, when processing an analog MUSE signal, it takes a long time to obtain a carry, so the pulse width of the internal frame pulse is wide, and when processing a digital MUSE signal, it takes a long time to obtain a carry. is short, so the pulse width of the internal frame pulse is short.

The internal frame pulse is supplied to one input terminal of the NAND circuit 411 of the out-of-synchronization detection circuit 41 and to the clock input terminal of the counter 412. The other input terminal of the NAND circuit 411 is supplied with an external frame pulse from the frame detection circuit 37. The output of this NAND circuit 411 is supplied to a clear terminal of a counter 412. The output of the counter 412 is supplied to one terminal of a NAND circuit 414, inverted by an inverter 413, and supplied to an enable terminal. The other input terminal of the NAND circuit 414 is supplied with an external frame pulse.

According to this out-of-synchronization detection circuit 41, if the phases of the internal frame pulse and the external frame pulse match, the counter 412 is cleared and its output is at a low level (
(no carry). Therefore, the output of the NAND circuit 414 maintains a high level. However, if the phases of the external frame pulse and the internal frame pulse do not match, the counter 412 will not be cleared. This causes the count to advance and a carry to be obtained. Therefore, at this time, the NAND circuit 41
The output of No. 4 becomes low level, and a detection signal indicating loss of synchronization is obtained. The output of this NAND circuit 414 is the first
It is supplied to the reset terminals of the filter 34, horizontal counter 38, and vertical counter 39 shown in the figure.

This invention is not limited to the above embodiments (, M
MUSE-T method that has the same synchronous waveform as the USE signal (Reference: 1988 Telecommunications Society Spring National Conference D-22-166)
Of course, it can also be applied to other receivers.

As explained above, according to this embodiment, the digital MU
Even during SE signal processing, it is possible to reliably detect out-of-synchronization, contributing to always obtaining good images.

FIG. 3 shows another embodiment of the invention.

Components that are the same as those in the embodiment shown in FIG. 1 are given the same reference numerals.

The parts that are different from the previous embodiment will be explained below.

In this embodiment, the window width setting circuit 40 sets the pulse width of the internal frame pulse to be slightly wider than the pulse width of the external frame pulse. The internal frame pulse output from the window width setting circuit 40 is input to one input terminal of the out-of-synchronization detection circuit 41.

The out-of-synchronization detection circuit 41 detects whether or not an external frame pulse exists within the pulse width of the internal frame pulse, and if it exists, it is in a synchronized state, and if it does not exist continuously for a certain period of time, it is in an out-of-synchronization state. Obtain the detection signal. In the out-of-synchronization state, the filter 34, horizontal counter 38, and vertical counter 39 are reset by the detection signal and set to the initial state. This will start synchronization pull-in from the beginning.

The output of the out-of-sync detection circuit 41 is also supplied to one input terminal of an AND circuit 53. The output terminal of this AND circuit 53 is connected to one input terminal 54D of the switch 54. The output terminal of the out-of-synchronization detection circuit 41 is directly connected to the other input terminal 54A of this switch 54. Moreover, the other terminal of the AND circuit 53 has
The output of a differentiating circuit 55 that differentiates the horizontal synchronizing pulse of the digital MUSE signal is supplied. The differentiating circuit 55 obtains an output signal in synchronization with the falling edge of one cycle width of the reproduced clock obtained from the voltage controlled oscillator 36 during the horizontal synchronization pulse period. The switch 54 is connected to the terminal 54D by a switching signal during digital MUSE signal processing. Therefore, the out-of-sync detection circuit 4
When the out-of-sync detection signal is obtained from 1, the digital MUS
A reset pulse for horizontal counter 38 will be provided when a horizontal synchronization pulse for the E signal is present.

According to the embodiment described above, during digital MUSE signal processing, the external and internal frame pulses are synchronized using the horizontal synchronization pulse as a reference, and when the internal frame pulse is out of synchronization, synchronization can be pulled in to an accurate phase. You can always get good images.

FIG. 4 shows yet another embodiment of the invention.

An analog MUSE signal including an HD signal and an external frame pulse is supplied to the input terminal 31 and digitized by an analog-to-digital (A/D) converter 32 . The digitized MUSE signal is input to a phase error detection circuit 33, where the phase error of the horizontal synchronization (l(D) signal) is detected.

For the horizontal synchronization signal, a phase detection point (HD point) is determined in advance as shown in FIG. Therefore, this H
If the sampling signal obtained at point D does not have a predetermined value, it means that the sampling pulse is out of phase, and the error output is input to the digital-to-analog (D/A) converter 35 via the filter 34. Ru. The output of the digital-to-analog converter 35 is supplied to one terminal of the switch 51. This switch 51 is an analog MUS
When processing the E signal, the terminal 51A is selected, and when processing the digital MUSE signal, the other terminal 51D is selected. A switching signal for this selection is supplied from terminal 43. An error signal from a switch 63, which will be described later, is supplied to the terminal 51D.

One input terminal 631 of the switch 63 receives the clock phase error output from the phase error detection circuit 44 through the filter 45.
Supplied via. The phase error detection circuit 44 detects the phase error of the external clock supplied to the clock input terminal CK of the digital human power section 42. In this case, the phase error detection circuit 44 uses the internal clock output from the voltage controlled oscillator 36 as a reference clock for phase comparison. Further, the other input terminal 632 of the switch 63 is supplied with the phase error output from the phase error detection circuit 65 via a filter 66 . The phase error detection circuit 65 detects the phase error of the external horizontal synchronization pulse supplied to the horizontal synchronization pulse input terminal H of the digital input section 42 . In this case, the phase error detection circuit 65 uses an internal horizontal synchronizing pulse from a reference pulse generation circuit (horizontal counter 38), which will be described later, as a reference pulse for phase error comparison.

Switching control of the switch 63 is performed by the output of the window comparator 67. Wind comparator 6
7 creates a switch control output according to the level of the clock phase output (output of the filter 45).

FIG. 5 shows the output of the filter 45 and the output of the window comparator 67. The window comparator 67 obtains an identification output in which the output level of the filter 45 is classified into three areas: high, medium, and low. Then, the switch 63 selects the output of the filter 45 when the output of the window comparator 67 indicates a level 631 in a large region or a small region, and selects the output of the filter 45 when the output of the window comparator 67 indicates a level 632 in a medium region.
Select and derive the output on the 6 side. The switch 63 outputs a clock phase error output when the clock phase error is large, and outputs a phase error of the horizontal synchronizing pulse when the clock phase error is small. The output of this switch 63 is supplied to the switch 510 input terminal 51D.

The output of the switch 51 is the voltage controlled oscillator 3 using a crystal.
6 control terminals. The oscillation output of the voltage controlled oscillator 36 is used as a sampling clock and as a pulse for creating internal horizontal synchronization pulses and internal frame pulses. That is, it is supplied to the horizontal counter 38.

This horizontal counter 38 obtains a horizontal address for each line, and its line count output (horizontal synchronization pulse) is also supplied to a vertical counter 39 and a phase error detection circuit 65. The vertical counter 39 obtains a vertical address and generates a VITSO frame pulse, that is, an internal frame pulse corresponding to an external frame pulse.

The internal frame pulse is input to the window width setting circuit 40. This window width setting circuit 40 sets 17 the pulse width of the internal frame pulse to be slightly wider than the pulse width of the external frame pulse.

The internal frame pulse output from the window width setting circuit 40 is input to one input terminal of the out-of-synchronization detection circuit 41.

Further, the output of the analog-to-digital converter 32 is supplied to one input terminal 52A of the switch 52. The other input terminal 52D of this switch 52 has a digital input section 4.
A digital MUSE signal from 2 is supplied. When processing the analog MUSE signal, this switch 52
When terminal 52A is selected and the digital MUSE signal is processed, control is performed by a switching signal from terminal 43 so that terminal 52D is selected.

The output of the switch 52 is input to a frame pulse detection circuit 37, where a predetermined pattern of external frames and pulses is detected. This external frame pulse is supplied to the other input terminal of the out-of-sync detection circuit 41.

The out-of-synchronization detection circuit 41 detects whether or not the pulse of the external frame pulse exists within the pulse width of the internal frame pulse, and if it exists, it is in a synchronized state, and if it does not exist continuously for a certain period of time, it is out of synchronization. Obtain a detection signal as the state. In the out-of-synchronization state, the filter 34, horizontal counter 38, and vertical counter 39 are reset by the detection signal and set to the initial state. This will cause synchronous pull-in to start from the beginning.

If the receiver is now switched to the digital MUSE signal processing state, the switch 51 will be in the state where the input terminal 51D side is selected, and the switch 52 will be in the state where the input terminal 52D side is selected. Phase error detection circuit 44, filter 45, switch 63.5
1. The phase-locked loop formed by the voltage controlled oscillator 36 functions as a loop that synchronizes the internal clock with the external clock. Further, a phase-locked loop formed by the phase error detection circuit 65, filter 66, switch 63.51, voltage-controlled oscillator 36, and horizontal counter 38 functions as a loop that synchronizes the internal horizontal synchronizing pulse with the external horizontal synchronizing pulse.

When the receiver is in the initial pull-in state of the synchronization signal, the error output of the phase error detection circuit 44 is large, so that the clock phase error information is used as the control information for the voltage controlled oscillator 36. This provides a high-speed retracting action. Then, when the stable state is reached, the switch 63
A phase control loop regarding the horizontal synchronizing pulse is formed, and synchronous reproduction is always performed in phase synchronization with the horizontal synchronizing pulse.

[Effects of the invention] As explained above, according to this invention, digital MUS
Both during E signal processing and digital MUSE signal processing, the synchronization state can be adjusted accurately, contributing to always obtaining good images.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the out-of-sync detection circuit and window width setting circuit of FIG. 1, and FIGS. 3 and 4 are respectively FIG. 5 is an explanatory diagram showing the operation of the window comparator and switch in FIG. 4. FIG. 6 is an explanatory diagram showing the structure of another embodiment of the invention. 7 is a diagram showing a synchronous regeneration circuit used in a conventional analog MUSE signal processing device, FIG. 8 is an explanatory diagram showing a signal format of the MUSE method, and FIG. 9 is a diagram showing a synchronous regeneration circuit used in a conventional analog MUSE signal processing device. FIG. 3 is an explanatory diagram of a synchronization signal included in the signal. 32...Analog-digital converter, 33.44.65
...Phase error detection circuit, 34.45.66...Filter, 35...Digital-to-analog converter, 36...
Voltage controlled oscillator, 37... frame pulse detection circuit,
38...Horizontal counter, 39...Vertical counter, 4
0...Window width setting circuit, 41...Out-of-synchronization detection circuit,
42...Digital input section, 51.52.63...Switch, 67...Window comparator. Applicant's agent Patent attorney Takehiko Suzue No. D

Claims (3)

[Claims] (1) In a receiver that can receive the MUSE method, which is a high-definition transmission method, the analog MUSE signal is digitized and the first MUSE
An analog-to-digital conversion means for outputting a signal; a digital input section to which the digital MUSE signal is supplied as a second MUSE signal and also its clock; and detecting a phase error of a horizontal synchronization signal included in the first MUSE signal. a first phase error detection means for detecting the phase error of the clock supplied to the digital input section; a first phase error detection means for detecting the phase error of the clock supplied to the digital input section; During signal processing, the first switch selects the output from the second phase error detection means and supplies it to the control terminal of the voltage controlled oscillator, and during analog MUSE signal processing, selects the first MUSE signal and supplies it to the control terminal of the voltage controlled oscillator. When processing the MUSE signal, a second switch selects a second MUSE signal and supplies it to the frame pulse detection circuit; and an external frame pulse detected by the frame pulse detection circuit using the output of the voltage controlled oscillator. means for generating an internal frame pulse for the first MU;
Frame pulse generation that creates an internal frame pulse with a width wider than the external frame pulse during SE signal processing, and sets the pulse width of the internal frame pulse to approximately the same width as the external frame pulse during second MUSE signal processing. means; out-of-synchronization detection means for detecting whether frame synchronization is out of order by comparing the phases of the external frame pulse and the internal frame pulse obtained by the frame pulse generation means; and from this out-of-synchronization detection means. . A high-definition receiver comprising: means for resetting the frame pulse generating means when an out-of-synchronization detection signal is obtained. (2) In a receiver that can receive the MUSE method, which is a high-definition transmission method, the analog MUSE signal is digitized and the first MUSE
an analog-to-digital conversion means for outputting a digital MUSE signal as a second MUSE signal; a digital input section to which a digital MUSE signal is supplied as a second MUSE signal and also its clock and horizontal synchronization pulse; a first phase error detection means for detecting a phase error; a second phase error detection means for detecting a phase error of the clock supplied to the digital input section; and a first phase error detection means when processing an analog MUSE signal. a first switch that selects the output from the second phase error detection means and supplies it to the control terminal of the voltage controlled oscillator when processing the digital MUSE signal; and a first switch that selects the output from the second phase error detection means when processing the digital MUSE signal; a second switch that selects a second MUSE signal and supplies it to the frame pulse detection circuit during digital MUSE signal processing; and a frame pulse generation means that generates an internal frame pulse using the output of the voltage controlled oscillator. and out-of-synchronization detection means for detecting whether frame synchronization is out of order by comparing the phases of the external frame pulse detected by the frame pulse detection circuit and the internal frame pulse obtained by the frame pulse generation means. , means for resetting the frame pulse generating means when an out-of-sync detection signal is obtained from the out-of-sync detection means, using the out-of-sync detection signal itself as a reset signal during the first MUSE signal processing; 1. A high-definition receiver comprising reset signal supply means that is switched to shape the horizontal synchronizing pulse of the digital input section and use it as a reset signal during second MUSE signal processing. (3) In a receiver capable of receiving the MUSE method, which is a high-definition transmission method, the analog MUSE signal is digitized and the first MUSE
an analog-to-digital conversion means for outputting a digital MUSE signal as a second MUSE signal; a digital input section to which a digital MUSE signal is supplied as a second MUSE signal and also its clock and horizontal synchronization pulse; a first phase error detection means for detecting a phase error; a second phase error detection means for detecting a phase error of a clock supplied to the digital input section; and a first phase error detection means for detecting a phase error of a clock supplied to the digital input section; The outputs of the third phase error detection means for detecting the phase error and the second phase error detection means are supplied through a filter, and an identification output is obtained that distinguishes the output level into three regions: high, medium, and low. a window comparator; and when the output of the window comparator indicates the level of the large area or the small area, the second
A first switch that selects the output of the phase error detection means of the second phase error detection means and selects and derives the output of the third phase error detection means when indicating the level of the middle region; 1 phase error detection means, a second switch that selects the output from the first switch during digital MUSE signal processing and supplies it to the control terminal of the voltage controlled oscillator; a third switch that selects a signal and, during digital MUSE signal processing, selects a second MUSE signal and supplies it to the frame pulse detection circuit; and a third switch that selects the second MUSE signal and supplies it to the frame pulse detection circuit; Comparison pulse generating means generates an internal frame pulse corresponding to the external frame pulse that corresponds to the external frame pulse, and also generates a reference pulse serving as a comparison standard in the second phase error detecting means and the third phase error detecting means; an out-of-synchronization detection means for detecting whether frame synchronization is out of order by comparing the phase of the pulse with the internal frame pulse obtained by the comparison pulse generation means; and an out-of-synchronization detection signal from the out-of-synchronization detection means A high-definition receiver comprising: means for resetting at least the comparison pulse generation means when the comparison pulse generation means is obtained.