JPH0435523A - Reference voltage generating circuit - Google Patents

Abstract

PURPOSE:To improve the stability of a reference voltage at the time of turning on a power source by providing a power-on reset circuit for outputting a pulse signal at the time of turning on the power source, and a start-up circuit for supplying a constant-current to emitters of each bipolar transistor in accordance with this pulse signal. CONSTITUTION:A start-up circuit 2 is controlled by an output of a power-on reset circuit 1, and an output terminal is connected to emitters of transistors QN1, QN2, respectively. The power-on reset circuit 1 generates a pulse signal only at the time of turning on a power source, and holds a stand-by state after the power source is turned on. The start-up circuit 2 is operated by a pulse signal inputted from the power-on reset circuit 1, and supplies a roughly equal current to the transistors QN1, QN2. Accordingly, a reference voltage generating part 10 starts to operate by a constant-current supplied from the start-up circuit 2, and reaches a stable circuit. In such a way, the stability of a reference voltage at the time of turning on the power source can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reference voltage generation circuit, and particularly to a bandgap reference type reference voltage generation circuit.

[Conventional technology] FIG. 5 is a circuit diagram showing a conventional reference voltage generating circuit.

As shown in Figure 5, a pair of p-type MO8) of the same size
The gates of the transistors MP, MP2 are connected to each other, and the sources are connected to the power supply VOO. On the other hand, pnp transistors QP with mutually different emitter areas
,,QP2 (emitter area: Q P 1 > Q P
2) has its base commonly connected to the bias power supply VB, and its collector connected to the ground GND. The emitters of the pnp transistors QP and QP2 are connected to the p-type MO8 through resistors R, R2 and R3, respectively.
) transistor MP1. Connected to the drain of MP2. The operational amplifier A1 is provided between the power supply VDD and the ground GND, its negative input is connected between the resistor R3 and the drain of the transistor MP2, and its positive input is connected between the resistor R1 and the resistor R2. , its output is fed back to the common gate of transistors MP, , MPa. The output terminal OUT is connected between the resistor R2 and the drain of the transistor MP.

In the reference voltage generation circuit configured as described above, the output of the operational amplifier A1 is fed back to the gates of the transistors MP, , MP, so that the reference voltage V REF between the bias power supply VB and the output terminal OUT is generated in a stable state.
It exhibits the characteristic that it remains approximately constant against changes in temperature and power supply voltage. Such characteristics are the result of transistor QP
I.

When a current equal to Q P 2 flows, the relationship between the emitter-base voltage VBEI of the transistor QP and the emitter-base voltage V BE□ of the transistor QP2 becomes stable as VBEI>VER2.

However, in this case, when the power is turned on, an equal current flows through transistors QPI and QP2 (I).As a result, the current in transistor QPQ becomes smaller, and the negative input of operational amplifier A1 becomes a lower voltage than the positive input, resulting in positive feedback. , it becomes increasingly difficult for current to flow through the transistor Q P 2.

In this case, the output voltage at the output terminal OUT is fixed at a certain specific voltage, and the circuit no longer functions as a reference voltage generation circuit. Therefore, a reference voltage generation circuit has been proposed which improves these drawbacks.

FIG. 6 shows a conventional reference voltage generation circuit (reference voltage generation section 11 indicated by a broken line) to which a startup circuit 2 is added.

The startup circuit 2 is configured as follows. p-type MoS transistor M P 3 .

MP4 has a source whose source is a transistor M P s −M
It is commonly connected to the sources of P2, and its drains are connected to the emitters of transistors QPI and QP2, respectively. And transistor MP3.

The gates of M P 4 are commonly connected to a bias power supply vIIT, and a constant bias voltage is applied thereto.

Note that the reference voltage generating section 11 is different from that shown in FIG. 5 in the arrangement of the resistors R1 to R3.

In the reference voltage generation circuit configured in this way, by supplying a constant current substantially equal to the transistors QP□ and QP2 from the startup circuit 2 before the feedback of the operational amplifier Ai is applied when the voltage is turned on, VB□>V□ It is intended to be 2.

By reducing the constant current supplied from the startup circuit 2 to a certain extent, the stability of the reference voltage VR□ when the power is turned on is improved, and the stability of the reference voltage VRIF against fluctuations in temperature and power supply voltage is excellent. It constitutes a reference voltage generation circuit.

[Problems to be Solved by the Invention] However, in the conventional reference voltage generation circuit described above,
The startup circuit 2 added to improve stability when the power is turned on is always on, even after reaching a stable state.
Since current continues to flow, there is a problem in that power consumption increases.

In addition, the transistor M constituting the startup circuit 2
P 32M P 4 element variation causes output terminal OU
There is a problem in that it directly affects the variation in the voltage value of the reference voltage vREF at T.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a reference voltage generation circuit that can improve the stability of a reference voltage when the power is turned on, reduce power consumption, and reduce variations in the reference voltage.

[Means for Solving the Problems] A reference voltage generation circuit according to the present invention includes a pair of bipolar transistors having different emitter areas, a resistor for converting the emitter current of each bipolar transistor into a voltage, and a resistor for converting the emitter current of each bipolar transistor into a voltage. In a reference voltage generation circuit having operational amplifiers for mutual comparison and a pair of MOS transistors that feed back the output of the operational amplifier to their gates and supply a constant current to each of the bipolar transistors, a pulse signal is output when the power is turned on. A power-on reset circuit to
The present invention is characterized by comprising a startup circuit that supplies a constant current to the emitter of each of the bipolar transistors in response to the pulse signal of the power-on reset circuit.

[Operations] In the present invention, an equal current is passed through a pair of bipolar transistors having different emitter areas, and a pair of MOs is used to supply a constant current to these bipolar transistors.
S) By feeding back the output of the operational amplifier to the gate of the transistor, the reference voltage generated between the bias power supply of the bipolar transistor and the drain of the MOS transistor is not affected by changes in temperature and power supply voltage, and is approximately remains constant. In this case, since the output of the operational amplifier is not fed back when the power is turned on, it is difficult for equal current to flow through the pair of bipolar transistors. The startup circuit supplies a constant current to the pair of bipolar transistors in response to a pulse signal output from the power-on reset circuit when the power is turned on. This makes it possible to improve the stability of the reference voltage when the power is turned on.

According to the present invention, since the startup circuit operates by the pulse signal supplied from the power-on reset circuit only when the power is turned on, the power-on reset circuit and the startup circuit are turned off in a stable state thereafter. be able to. Therefore, power consumption can be significantly reduced. Furthermore, even if there are variations in the elements of the transistors that constitute the power-on reset circuit and the startup circuit, in a stable state, these variations do not directly affect the reference voltage.

[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a reference voltage generation circuit according to a first embodiment of the present invention.

The reference voltage generating section 10 is configured as follows.

nl) n) transistor QN with mutually different emitter areas
I, QNQ (emitter area: QN.

>QN2) has its base commonly connected to the bias power supply VB, and its collector connected to the power supply VDD.

On the other hand, a pair of n-type MO8) transistors MN, MN2 have their gates connected to each other and their sources connected to the ground GN.
Connected to D. Then, the drains of the n-type MO8) transistors MN, MNQ are connected to the npn) transistors Q N t , Q through resistors R1, R2 and resistor R3, respectively.
It is connected to the emitter of Nt. The operational amplifier A is provided between the power supplies Vf, D and the ground GND, its negative input is connected between the resistors R1 and R2, and its positive input is connected between the resistor R3 and the emitter of the transistor QN2. and its output is connected between the transistors M N s
−M N t common gate.

The output terminal OUT is a resistor R8 and a transistor MN.

connected between the drain and the drain. In this way,
By applying negative feedback to the common gate of transistors MN, MN2, the voltage value taken out from the output terminal OUT connected to the drain of transistors MN, (or MN2) will be different from the voltage applied to the bases of transistors QN, , QNQ. It is configured to be constant.

The startup circuit 2 is controlled by the output of the power-on reset circuit 1, and its two output terminals are connected to the emitters of the transistors QN, QN2, respectively. The power-on reset circuit 1 generates one pulse signal only when the power is turned on, and maintains a standby state after the power is turned on. The startup circuit 2 is operated by a pulse signal inputted from the power-on reset circuit 1 when the power is turned on, and includes transistors QN,.

A current approximately equal to Q N 2 is supplied. Therefore, the reference voltage generating section 10 starts operating with the constant current supplied from the startup circuit 2, and reaches a stable state.

According to this embodiment, since the startup circuit 2 is operated by the pulse signal supplied from the power-on reset circuit 1 only when the power is turned on, the power-on reset circuit 1 and the startup circuit 2 are operated in a stable state after the power is turned on. Can be placed on standby. Therefore, power consumption can be significantly reduced, and in particular, when configured with a 0M08 circuit, the current consumption can be reduced to the same level as the leakage current. Further, even if there are variations in the elements of the transistors constituting the power-on reset circuit 1 and the startup circuit 2, in a stable state, this variation does not directly affect the reference voltage VREF at the output terminal OUT.

FIG. 2 is a circuit diagram showing a reference voltage generating circuit according to a second embodiment of the present invention. In this embodiment, a power-on reset circuit is added to the conventional circuit shown in FIG.
Onricera! - Since the startup circuit is controlled by the circuit, the same reference numerals are given to the same parts and detailed explanation of the parts will be omitted.

This embodiment is based on the nl)n) transistor QN! in the first embodiment. , ON2 and n-type MO8) transistor MN
,,In place of MN2, respectively I) n I) l-randisk QP, , QP2 and p-type MO8) transistor MPi
, MP2 is used, and the reference voltage generating section 11 is configured by switching the relationship between the power supply Vno and the ground GND. Therefore, the polarity of the output terminal OUT can be reversed from that in the first embodiment. In this case, the same effects as in the first embodiment can be obtained by reversing the polarities of the power-on reset circuit 1 and the startup circuit 2 from those in the first embodiment.

FIG. 3 is a circuit diagram showing a reference voltage generation circuit according to a third embodiment of the present invention. This embodiment is a further embodiment 1 of the second embodiment shown in FIG. 2.The reference voltage generation section 12 includes a p-type MO8) in addition to the reference voltage generation section j1 in FIG. Transistor MP5, MPB
and diode QP3. QP4 is used. The transistors MP, MP6 have their gates connected to each other, their sources connected to the power supply VDr), and their drains connected to the ground GND via diodes QPs and QP4, respectively.
It is connected to the. Also, transistors MP, , MP2
Similarly, the output of the mechanical amplifier A1 is fed back to the common gate of the transistors MPa and 1MPe.

The bases of the transistors QP, , QP2 are separated from each other by diodes QP, respectively.

Connected to the node side of QP4. In this way, the bias voltage of the transistors QPi and QP2 is supplied from the power supply VDD according to the feedback output of the operational amplifier A1, so the reference voltage RI at the output terminal OUT is connected to the ground GND.
It is possible to generate a predetermined voltage value for each time, and
By increasing the voltage values of the positive and negative inputs of operational amplifier A+, stable operation of operational amplifier A can be maintained.

On the other hand, the startup circuit 2 is configured as follows. The p-type MO8) transistors MP3 and MP4 have their gates connected to each other, their sources connected to the power supply VDD, and their drains connected to the transistors QP1...MP4, respectively. Q
Connected to the emitter of P2. The gates of the p-type MO8) transistors MP7゜MP are connected to each other,
Its sources are connected to the power supply ■DD, and its drains are respectively connected to diodes QP3. QP is connected to the anode of QP. 6. Transistor MP3, MP.

The output signal of the power-on reset circuit 1 is supplied to the gates of MP, , MP8, respectively, and the output signal of this signal is
It is controlled by N or OFF.

The power-on reset circuit 1 is configured as follows. Two types of n-type MO8I transistors MN pulled up by the power supply VDD! I, MN4 is grounded GN
D are sequentially connected in cascade. Transistor MN4. M
A capacitor IC2 is connected between the drains of N and the ground GND. Further, a capacitor CI is connected between the source of the transistor MN4 and the power supply VD+. n
type MO8) transistor M N 3 and p-type MO3) transistor MP.

are connected in a complementary pair between the power supply VDD and the ground GND, forming an inverter circuit. This l transistor M
N 3. M Pe has its gate commonly connected to the source of the transistor MN4, and supplies an output signal to the startup circuit 2 from between both drains.

According to this embodiment, in the power-on reset circuit 1, the electric charge instantaneously charged in the capacitor C1 when the power is turned on is gradually discharged through the transistors MN4, MN and the capacitor C2. First, during charging, the transistor MN3
Since the inverter circuit consisting of 1 MPs has its gate input exceeding the threshold voltage, it lowers its output signal to a low level. Therefore, transistor MP3-
MP4.

MP? 9M Pa starts its drain current to flow, and supplies a constant current to the reference voltage generation section 12. Then, during discharging, transistor MN3. The inverter circuit consisting of MPs pulls its output signal to high level since its gate input crosses the threshold voltage again. Therefore, transistors MP3, MP4, MP
7. MPs is in the OFF state, and the reference voltage generator 12
Stop supplying constant current to. In this way, when the power is turned on, a constant current is supplied from the startup circuit 2 controlled by the power-on reset circuit 1 to the reference voltage generation section 12. Further, in the stable state after that, the power-on reset circuit 1 and the startup circuit 2 enter the standby state.

FIG. 4 is a signal waveform diagram of the reference voltage generating circuit shown in FIG. 3. Note that point a and point b indicate arbitrary points at the input end and output end of the inverter circuit (transistor MN3.MPe), respectively.

As shown in FIG. 4, when the power supply (vf, D) is turned on, the point a reaches a high level due to charging of the capacitor C1, and then is discharged and gradually lowers to a low level. At this time, point b (output point of power-on reset circuit 1) becomes low level in accordance with the threshold voltage of the inverter circuit.

Therefore, during this period, transistors MP3, MP4゜M
Since the drain currents of P7 and MP flow, and the feedback by the operational amplifier A1 in the reference voltage generating section 12 becomes negative feedback, the output waveform of the output terminal OUT is easily stabilized at the reference voltage VRE.

[Effects of the Invention] As explained above, according to the present invention, a pulse signal is output from the power-on reset circuit when the power is turned on, and the startup circuit is operated in accordance with this pulse signal.
The stability of the reference voltage when the power is turned on can be improved. Furthermore, in a stable state after the power is turned on, the power-on reset circuit and the startup circuit are in the OFF state, so power consumption can be significantly reduced, and variations in the elements of the power-on reset circuit and startup circuit can be reduced. Variations in the reference voltage can be reduced without affecting the reference voltage.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a reference voltage generation circuit according to a first embodiment of the invention, FIG. 2 is a circuit diagram showing a reference voltage generation circuit according to a second embodiment of the invention, and FIG. 3 is a circuit diagram showing a reference voltage generation circuit according to a second embodiment of the invention. A circuit diagram showing a reference voltage generation circuit according to a third embodiment of the present invention, FIG. 4 is a signal waveform diagram thereof, FIG. 5 is a circuit diagram showing a conventional reference voltage generation circuit, and FIG. 6 is a circuit diagram showing other conventional reference voltage generation circuits. FIG. 2 is a circuit diagram showing a reference voltage generation circuit of FIG.

Claims (1)

[Claims] (1) A pair of bipolar transistors with different emitter areas, a resistor that converts the emitter current of each bipolar transistor into a voltage, an operational amplifier that compares this voltage with each other, and the output of the operational amplifier is fed back to its gate. and a pair of MOS transistors that supply a constant current to each of the bipolar transistors. A reference voltage generation circuit comprising: a startup circuit that supplies a constant current to the emitter of each of the bipolar transistors according to the startup circuit.