JPH0435535A - Data transmission method - Google Patents

Abstract

PURPOSE:To exactly and easily the serial transmission of data by setting a first synchronizing section to a first voltage level, setting a second synchronizing section to a second voltage level, setting each bit in a data section to a first or a second voltage level, and setting time width of a first synchronizing section larger than time width of the data section. CONSTITUTION:A unit signal consists of a first synchronizing section Ta, plural data sections Tc containing plural bits, and a second synchronizing section Tb placed adjacently in its end. A first synchronizing section Ta is in a first voltage level, a second synchronizing section Tb is in a second voltage level being different from a first voltage level, each bit in the data section Tc is in a first or a second voltage level, and also, time width of a first synchronizing section Ta is set larger than time width of the data section Tc. Accordingly, by a difference between the time width of a first synchronizing section Ta and the time width of the data section Tc, a first synchronizing section Ta and the data section Tc, data in the data section Ta can be read exactly. In such a way, the serial transmission of data can be executed exactly and easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission method that allows measurement digital data and the like to be transmitted with high reliability through one transmission path.

[Prior Art and Problems to be Solved by the Invention] Transmitting or recording serial signals combining data bits and clock bits has already been practiced. However, with conventional methods, it is difficult to extract data accurately and easily.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a data transmission method capable of accurately and serially transmitting data to a container.

[Means for Solving the Problems] To achieve the above object, the present invention provides a method for repeatedly transmitting a unit signal consisting of data and a synchronization signal.
The unit signal includes a first synchronization period, a plurality of data periods each including a plurality of bits, and a second synchronization period arranged adjacent to each end of the plurality of data periods, and a second voltage level in which the synchronization interval is at a first voltage level, and the second synchronization interval is different from the first voltage level;
, and each bit of the data interval is at the first or second voltage level, and the time width of the first synchronization interval is set to be larger than the time width of the data interval. The present invention relates to a data transmission method characterized by the following.

Note that when the time width of the data section is nXTl (where n is the number of bits and T1 is the time width of 1 bit), the first
It is desirable that the time width of the second synchronization interval be (n+1)XT1 and the time width of the second synchronization interval be TI.

[Function] According to the above invention, the first synchronization interval can be easily and accurately detected based on the difference between the time width of the first synchronization interval and the time width of the data interval. Therefore, it is possible to accurately distinguish between the first synchronization interval and the data interval, and to accurately read the data in the data interval.

[Embodiment] Next, a data transmission system according to an embodiment of the present invention will be explained.

In this embodiment, a serial signal shown in FIG. 3(A) is formed and transmitted from the transmitting side to the receiving side using one signal line. The serial signal in FIG. 3(A) is an arrangement in which unit signals are repeated at a period T.

The unit signal has a first synchronization period (leading pulse period) Ta at a low level (first voltage level), a second synchronization period Tb at a high level (second voltage level), and a signal from a low level or a high level. It consists of a data section Tc.

The first synchronization period Ta occurs repeatedly with a period T, and the second synchronization period Tb is arranged adjacent to a plurality of (three) data periods TcO.

Each data interval Tc is nXT1 to transmit n bits.
(here, TI has a time width of 1 bit). The first synchronization period Ta has a time width of (n + l) XTI, and the second synchronization period Tb has a time width of T1. In this example, n is 7, so Tc is 7TL
, Ta is 8Tl, and Tb is T1. The first of the three data intervals Te is adjacent to the third synchronization interval Ta. A second synchronization period Tb is arranged between the first, second, and third data periods TC, and a second synchronization period Tb is also arranged between the third data period TC and the first synchronization period Ta of the next cycle. Two synchronization sections Tb are arranged.

The serial signal of FIG. 3A is formed by the transmitting circuit of FIG. This transmitting circuit includes a 21-bit measurement data generation circuit 1, a 21-bit latch circuit 2, a data selector 3 consisting of a 32-bit multiplexer, and an IMH.
z oscillator 4 and an address counter 5.

A 21-bit parallel output line of the measurement data generation circuit 1 is connected to a latch circuit 2. The latch circuit 2 latches (holds) input data for a certain period of time and outputs it.

The data selector 3 has first to 32nd input terminals A1 to A3.
2, the first to eighth input terminals A1 to A8 are connected to the ground terminal 6 for providing a first voltage level (low level), and the ninth to fifteenth input terminals A9 to A15, 1
7th to 23rd input terminals AI7 to A23 and 25th to 3rd input terminals
1 input terminals A25 to A31 are connected to the first to 21st output terminals of the latch circuit 2, and the 16th, 24th, and 32nd
Input terminals A16, A24, and A32 of are connected to a power supply terminal 7 that provides a second voltage level (high level).

The address counter 5 counts the output pulses of the I MHz'z oscillator 4 to form an address signal (selection signal) for the data selector 3 and sends it to the data selector 3. Since the address signal has a period T, the signals at the input terminals A1 to A32 of the data selector 3 are selected periodically. That is, in the data selector 3, the first to eighth input terminals A1
By selecting ~A8, t1 in FIG. 3(A)~
An 8-bit low level signal of the first synchronization interval Ta of t2 is formed and sent to the output terminal 8. Next, the 9th to 1st
5, the first data interval Tc from t2 to t8 in FIG. 3(A) is selected.
7-bit data is selected and sent to output terminal 8. Next, the input of the 16th input terminal AlB is selected,
A high level signal TbO in the second synchronization period from t3 to t4 in FIG. 3(A) is sent to the output terminal 8. By sequentially selecting the inputs in this manner, the serial signal shown in FIG. 3(A) is obtained.

The serial signal in FIG. 3(A) is transmitted from the output terminal 8 in FIG. 1 to the input terminal 11 of the receiving circuit in FIG. 2 via a single signal transmission line 10 such as a wired, wireless, or optical transmission line. It will be done. The receiving circuit includes a shift register 12, a latch circuit 13, and an 8M
Hz oscillator 14 and first synchronization section end detection circuit 15
, a shift register clock signal and latch strobe signal generation circuit 16 , and a malfunction detection circuit 17 .

The first synchronization period end detection circuit 15 includes a counter 18, the serial signal input terminal 11 is connected to the clear terminal CL, and the oscillator 14 is connected to the clock input terminal IN. Note that the oscillation frequency of the oscillator 14 is higher than the oscillation frequency (IMHz) of the transmitting side oscillator 4, and the periods of the output pulses of both oscillators 4 and 14 are sufficiently longer than the bit period T1 of the serial signal in FIG. 4(A). short.

Since the counter 18 is configured to be cleared when the clear terminal CL is at a high level, it measures the period during which the serial signal is low and veiled. The counter 18 is nXT1 <Tal< (n+1)XTI, that is, 7
Tl<Tal<8 When the output of the oscillator 14 is counted continuously during the time Tal satisfying Tl, the first synchronization section end detection pulse shown in FIG. 3(B) is generated on the line 18a. In short, the serial signal becomes low level at time t1 in FIG. 3(A), and when this low level continues continuously for an 8-bit period, the pulse shown in FIG. 3(B) is generated. Even if all 7 bits of data are at low level in the data interval from t4 to t5, the pulse of FIG. 3B is not generated on line 18a because the low level period is not longer than 7Tl. Therefore, the first synchronization period can be detected reliably and easily.

The shift register clock signal and latch strobe signal generation circuit 16 also includes a counter 19, whose input terminal IN is connected to the oscillator 14. The clear terminal CL of the counter 19 at the subsequent stage is connected to the output line 18a of the counter 18 at the previous stage. The output line 19a of the counter 19 receives the shift register clock signal shown in FIG. 3(C), and the output line 19b receives the shift register clock signal shown in FIG.
) latch strobe signal can be obtained. That is, after counting Tl/2 from the trailing edge (falling edge) of the pulse in FIG. 2(B), a high level pulse with width T1/2 is generated, and T1
After counting /2, a high level pulse with a width T1/2 is generated. In short, the clock pulse shown in FIG. 3(C) is generated at period T1 and applied to the clock terminal CK of the shift register 12. The shift register 12 is shown in Fig. 3 (A).
The serial signal is read in synchronization with the leading edge (falling edge) of the clock pulse in FIG. 3(C). Since the leading edge of the clock pulse in FIG. 3C is located approximately in the center of each bit in FIG. 3, each bit is accurately read.

The counter 19 receives the clock pulse of FIG. 3(C) by l/8.
A latch strobe signal corresponding to a pulse whose frequency is divided into 1 and 2 is generated as shown in FIG. 3(D).

That is, a high-level pulse is generated at t9, 8 Tl after the time t8 when counting of 3 (Tc + Tb ) = 24 TI is completed from the trailing edge of the first synchronization section end detection pulse in FIG. 3(B). This pulse in Fig. 3(D) is as shown in Fig. 3(A).
This almost coincides with the first synchronization period Ta.

The latch circuit 13 in FIG. 2 is connected to the output line 1 of the counter 19.
The contents of the shift register 12 are read in synchronization with the leading edge (rising edge) of the strobe signal 9b.

For example, at time t8 in FIG. 3, the shift register 12 holds a 24-bit signal for the period t2 to t8. These 24-bit signals are then simultaneously transferred to the latch circuit 13. t3~t4, t5~tri, t7~
Although the second synchronization signal bit in the t8 period is unnecessary as data, in this embodiment, it is read into the latch circuit 13 at the same time as the data bit in order to detect malfunction or normal operation.

The first to twenty-fourth output terminals 81 to B24 of the latch circuit 13
The 8th, 16th, and 24th output terminals B8, BlB, and B2 of
By extracting the 21-bit output D1 to D21 excluding the output 4, the three data sections Tc in FIG.
It is possible to output data corresponding to all bits in parallel.

The malfunction detection circuit 17 detects transmission abnormalities due to disconnections, short circuits, etc. in the transmission line 10.
a and a latch circuit 17b for this output. The counter 17a has a low level period of 2T for the serial signal at the input terminal 11.
a, that is, when it exists continuously for 16TI or more, an abnormal output is generated, and this is latched by the latch circuit 17b. That is, even if all bits in the data section from t2 to t8 in FIG. 3(A) are at low level during normal operation,
The continuous period of low level is Ta + Tc - 15TI.

Therefore, when the counter 17a detects 16TI, it means that the bit of the second synchronization period Tb in the period t8 to t4 cannot be detected. Failure to receive bits in the second synchronization period Tb means a transmission error.

This embodiment has the following effects.

(1) By using the data format shown in FIG. 3(A), data transmission through one transmission path 11 can be achieved accurately and easily.

(2) The first synchronization period Ta and the second voltage level
By arranging the second synchronization period Tb of the voltage level as shown in FIG. 3(A), data bits can be accurately determined and abnormalities can be easily detected.

(3) By configuring the transmitting circuit as shown in FIG. 1, the bit arrangement shown in FIG. 3(A) can be easily achieved.

(4) By forming the receiving circuit as shown in FIG. 2, data detection can be performed easily and accurately.

(5) Malfunctions can be easily detected by the malfunction detection circuit shown in FIG.

[Modifications] The present invention is not limited to the above-described embodiments, and, for example, the following modifications are possible.

(1) As shown in FIG. 4, the malfunction detection circuit 17 can be constructed of an inverter 1yad connected to the input terminal 11, a counter 17e that uses this high-level output as a clear input, and a latch circuit 17f. can. In this case, the counter is t2-t8 period 3 (Tc+Tb)− in FIG.
It is determined whether the serial signal is at a high level continuously for a longer time than 2471. That is, even if all three data sections Tc in FIG. 3(A) are at a high level, 24
After the period T1 has elapsed, there is a first synchronization period with a low level, so in a normal state, the signal becomes a low level signal after 24T1, and no abnormal output is generated from the counter 17e. Note that abnormality detection may be performed by combining both the malfunction detection circuits 17 shown in FIG. 2 and FIG. 4.

(2) A normal operation determination circuit shown in FIG. 5 can be provided. The circuit of FIG. 5 comprises a first synchronization period time width determining circuit 21 connected to line 19b of FIG. 2 and an AND gate 22. The time width determination circuit 21 is shown in FIG. 3(D).
It is determined whether the time width of the first synchronization interval is Ta-8TI.

The AND gate 22 is connected to the output of the time width determination circuit 21, and is also connected to the output terminal B8 of the latch 13 in FIG.
It is connected to B1ft and B24. This allows the first
It becomes clear whether the synchronization interval Ta and the second synchronization interval Tb exist normally, and normal operation (malfunction) can be known.

(3) In FIG. 3A, three data sections Tc are arranged in the unit signal section T, but the number of data sections Tc can be increased or decreased. Furthermore, in the embodiment, one word is transmitted in a unit signal interval T with a total of 21 bits in three data intervals TC, but one period T may include a plurality of words.

(4) The first synchronization period Ta can be set to a high level, and the second synchronization period Tb can be set to a low level.

(5) Although the latch circuit 2, data selector 3, second shift register 12, and latch circuit 13 in FIG. 1 are shown as one block, they may be configured by a combination of a plurality of individual circuit elements.

[Effects of the Invention] As described above, according to the present invention, data can be transmitted in series accurately and easily.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data transmitting circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a data receiving circuit according to an embodiment of the present invention, and FIG. 3 shows the state of each part in FIG. The waveform diagrams shown in FIGS. 4 and 5 are block diagrams showing modifications of the malfunction or normal operation detection circuit, respectively. 3...Data selector, 10...Transmission line, 12...
・Shift register, 13... latch circuit. Figure 1 Address: 4-11-10 Ogikubo, Suginami-ku, Tokyo Address: 169 Amended. 2. Claims [1] A method for repeatedly transmitting a unit signal consisting of data and a synchronization signal, wherein the unit signal includes a first synchronization period, a plurality of data periods each including a plurality of bits, and a first synchronization period, a plurality of data periods each including a plurality of bits, and a second synchronization period disposed adjacent to each end of a plurality of pig periods, and the first synchronization period is at a first voltage level, and the second synchronization period is at the first voltage level. and each bit of the data interval is at the first or second voltage level, and the width of the first synchronization interval is equal to the time of the data interval. A data transmission method characterized by being set larger than the width. [2] Each of the plurality of data intervals has a time width of nXTl (iuLTI is a transmission time width of 1 bit) in order to transmit n bits, and the first synchronization interval has a time of (n + 1) XTI. 2. The data transmission method according to claim 1, wherein the second synchronization interval has a time width of TI.

Claims (1)

[Claims] [1] A method for repeatedly transmitting a unit signal consisting of data and a synchronization signal, wherein the unit signal includes a first synchronization period, a plurality of data periods each including a plurality of bits, and a first synchronization period, a plurality of data periods each including a plurality of bits, and a second synchronization period disposed adjacent to each end of a plurality of data periods, and the first synchronization period is at a first voltage level, and the second synchronization period is at the first voltage level. and each bit of the data interval is at the first or second voltage level, and the time width of the first synchronization interval is greater than the time width of the data interval. A data transmission method characterized by a large setting. [2] Each of the plurality of data intervals has a time width of n×T1 (where T1 is a transmission time width of 1 bit) in order to transmit n bits, and the first synchronization interval has a time width of (n+1)×T1. A data transmission method, wherein the second synchronization period has a time width of T1.