JPH0435574A - Vertical synchronizing signal separating circuit - Google Patents

Abstract

PURPOSE:To improve the general usefulness, to simplify the circuit constitution, and to improve the precision of separation timing by counting a vertical synchronizing pulse, a vertical synchronism period, and the number of vertical synchronizing pulses in the vertical synchronism period in accordance with synchronizing pulses included in a television signal. CONSTITUTION:First to third count values DREF1 to DREF2 are set in accordance with a desired television signal VD0 by count value setting means (register circuits) 4, 10, and 12, and a clock SCK is counted up to the first count value DREF1 by a first counting means (vertical synchronizing pulse detecting circuit) 3 in accordance with synchronizing pulses PM3 and PV3 included in the television signal VD0 to detect the vertical synchronizing pulse PV3. A second counting means (vertical synchronism period detecting circuit) 7 performs counting up to the second count value DREF2 after the timing of the first vertical synchronizing pulse PV3 to detect a vertical period SV, and a third counting means (vertical synchronizing signal detecting circuit) 11 counts the number of vertical synchronizing pulses PV3 up to the third count value DREF3 for the vertical synchronism period SV. Thus, the general usefulness is improved, and the circuit constitution is simplified, and the precision of separation timing is improved.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A: Industrial field of application B: Overview of the invention C: Prior art (Figs. 4 and 5) D: Problems to be solved by the invention 11 (Figs. 4 to 6) 8
Means for Solving the Problems (Fig. 1) F Effects (Fig. 1) G Embodiments (Figs. 1 to 3) H Effects of the Invention A Industrial Application Field The present invention relates to a vertical synchronization separation circuit. In particular, the present invention can be applied to digital signal processing circuit configurations that separate vertical synchronization signals of various television signals.

B. Summary of the Invention The present invention sets first, second, and third count values in a vertical synchronization separation circuit according to a desired television signal, and sets a clock in accordance with a synchronization pulse included in the television signal. A vertical synchronization pulse is detected by counting up to a first count value, and a vertical synchronization period is detected by counting from the timing of the first vertical synchronization pulse to a second count value, and the number of vertical synchronization pulses in this vertical synchronization period is By counting up to the third count value, vertical synchronization signals of various television signals can be detected.

C. Prior Art Conventionally, in a television receiver of a television receiver or a video recorder, a vertical synchronization separation circuit is used to separate a vertical synchronization signal contained in a television signal.

As such a vertical synchronization separation circuit, one having an analog signal processing circuit configuration is generally used.

That is, in the analog vertical synchronization separation circuit, as shown in FIG. 4(A), the video signal Sv! included in the television signal VDsysc, which is an inverted version of the television broadcast signal of the NTSC television system, for example. Synchronous pulse P other than l. s and PVs are sequentially integrated, and the resulting integrated signal I MtNC (Fig. 4 (B)) is equal to the predetermined value VTH.
Vertical synchronization signal Vsyxc (fourth
(C)).

However, such a vertical synchronization separation circuit requires a large number of analog signal processing circuits such as an integrating circuit and a comparison circuit, resulting in a large number of components, and also has the problem of poor separation timing accuracy of the vertical synchronization signal.

Therefore, instead of an analog type vertical synchronization separation circuit, a vertical synchronization separation circuit having a digital signal processing circuit configuration has been used to reduce the number of parts and improve separation timing accuracy.

In practice, this digital vertical synchronization separation circuit consists of, for example, two
The first counter circuit receives the television signals VD and A as shown in FIG. 5(A). The counting operation starts at the timing when the synchronization pulses pMs and Ps+3 included in the synchronization pulse pMs and Ps+3 fall.
It is reset at the timing when us and P VS rise.

Further, this first counter circuit has a clock 5e having a cycle shorter by a predetermined period than the falling period of the horizontal synchronizing pulse pws.
A counting operation is performed at x (FIG. 5(B)), and at the timing when the count reaches a predetermined count value, a vertical synchronizing pulse detection signal 5vs (FIG. 5(C)) is sent to the second counter circuit.

This second counter circuit sequentially counts the input vertical synchronizing pulse detection signal Sv3, and at the timing when it has counted up to a predetermined count value, the vertical synchronizing signal detection signal Vs
yHc (FIG. 5(D)), thus making it possible to separate the vertical synchronizing signal with a relatively simple circuit configuration and high separation timing accuracy.

Problems to be Solved by the Invention In general, in the television broadcast signal VDNtse+ (VDstscz) of the NTSC television system, the horizontal synchronization period (1) is as shown in FIG. 6(A).
It has a vertical synchronization period (3H) that is three times as long as 1), and the equalization pulse is applied for 3H minutes before the vertical synchronization period and 3H or 3.5H minutes after it (Fig. 6 (B)), which differs from field to field. It is formed.

On the other hand, in the television broadcast signal VDpat of the PAL television system, the synchronization pulses PM31 and Pvs+ are in the horizontal synchronization period (I
It has a vertical synchronization period (2.5H) that is 2.5 times as long as H), and equalization pulses are formed 2.5H minutes before and 3H or 3.5H minutes after the vertical synchronization period.

In addition, in the television broadcast signal VDMD of the studio standard high-definition television system, Fig. 6 (
As shown in D), the three-value synchronization pulse P Msle, P
VSIO, has a vertical synchronization period (5H) that is five times the horizontal synchronization period (IH), and has a horizontal synchronization pulse P. ,
. Its own frequency is about twice as high as that of the NTSC television system.

In this way, there are various types of television broadcast signals VDN? When separating the vertical synchronization signal from 3e, vDPAL, and D0, if the analog vertical synchronization separation circuit described above is used, it is considered that the comparison voltage VTN for the integral signal I5YHC can be arbitrarily set.

However, in the same case, in the digital vertical synchronization separation circuit described above, the clock frequency and count value of the first counter circuit are changed depending on the frequency of the horizontal synchronization pulse pNs and the falling period of the vertical synchronization pulse Pvs.
It was necessary to change the circuit configuration itself, such as changing the count value of the second counter circuit according to the number of vertical synchronization pulses pvs during the vertical synchronization period, and the versatility was still insufficient.

The present invention has been made in consideration of the above points, and proposes a vertical synchronization separation circuit that can significantly improve versatility, and can separate vertical synchronization signals with a relatively simple circuit configuration and high separation timing accuracy. This is what I am trying to do.

8 Means for Solving the Problems In order to solve the problems, in the present invention, depending on the desired television signal VD, the horizontal synchronization pulse PM of the television signal VD is made longer and the vertical synchronization pulse P master is made longer. The first count value D□ corresponding to a period shorter than 3
A second count value D□ corresponding to the vertical synchronization period of Fl and the television signal VD. and a third count value D□ according to the number of vertical synchronization pulses pws included in the vertical synchronization period.

count value setting means 4.10.12.21 for setting the horizontal synchronizing pulse P included in the television signal VD.
From the timing when the front edge of H1 and the vertical synchronizing pulse pvsO is detected, the clock S0 with a shorter cycle than the horizontal synchronizing pulse pHs is counted up to the first count value D□□, and the vertical synchronizing pulse detection signal S V31 is sent out, or the horizontal Synchronous pulse P. The first counting means 3 is reset at the timing when the trailing edge is detected, and the predetermined clock 5CKI is set to the second count value D□ from the timing of the first vertical synchronizing pulse detection signal Svs+. A second counting means 7 detects the vertical synchronization period Sv by counting up to
is the third count value D□. A third counting means 11 is provided for counting up to the vertical synchronizing signal VMYWC of the television signal VD.

The first, second and third count values D0□, D, E, and DlltF depend on the desired television signal VD.
1, the clock S0 is counted up to the first count value , , , according to the synchronizing pulses P, 43, pvs included in the television signal VD0, and the vertical synchronizing pulse p is set.
VS is detected, and the second count value is calculated from the timing of the first vertical synchronization pulse pVS...! The vertical synchronization period Sv is detected by counting up to
VO vertical synchronization pulse P VS number as third count value D
I! By counting up to F3, the vertical synchronization signal V3YNC of various television signals VD,
can be detected.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, reference numeral 1 generally indicates a digital vertical synchronization separation circuit according to the present invention, in which, for example, a television signal VD, which is an inversion of a television broadcast signal of the NTSC television system, is transmitted to a clock synchronization circuit 2 together with a predetermined clock signal S0. As a result, the clock signal 5e11
The television signal VD whose phase is aligned with the vertical synchronization pulse detection circuit 3 is input to the vertical synchronization pulse detection circuit 3.

This vertical synchronization pulse detection circuit 3 consists of a counter circuit 3A and a comparison circuit 3B, and the television signal VD is input to the clear input terminal of the counter circuit 3A, and the clock signal 5 is input to the clear input terminal of the counter circuit 3A.
ell is input to the count input terminal.

As a result, this counter circuit 3A receives the television signal V.
Sync pulses P0 and P other than video signal S0 included in D.
The clock signal S0 is counted during the falling period of VJ, and the resulting count value DeNTl is input to the following comparison circuit 3B.

The comparison circuit 3B compares the count value DCNtl inputted from the counter circuit 3A with the value of the first reference value data I)at□ set in the first register circuit 4, and the count value DCN□ is determined as the first reference value. Value data DI! A vertical synchronizing pulse detection signal 5vss that rises and falls at the same timing as , is generated, and is sent to the continuous detection circuit 5 and the first
The signal is sent to the latch circuit 6.

Here, for the first reference value data D□, a predetermined value is selected such that the count value D0□ is longer than the falling period of the horizontal synchronizing pulse pHw and shorter than the falling period of the vertical synchronizing pulse PM3. The vertical synchronization pulse detection signal SVS+ is obtained by detecting the pulse p+ts.

Further, the vertical synchronization pulse latch signal Rvs, which is latched by the first latch circuit 6 and is made to rise until it is reset, is transmitted to the vertical synchronization period detection circuit 7 and the frame window count circuit 9 of the framing processing circuit 8 provided therein. has been entered.

The vertical synchronization period detection circuit 7 consists of a counter circuit 7A and a comparison circuit 7B, and the vertical synchronization pulse latch signal Rma 3 is inverted and inputted to the clear input terminal of the counter circuit 7A, whereby the first vertical synchronization pulse detection signal 5vst The clock signal S0 is counted from the timing of , and this count value Dcwrx is sent to the comparison circuit 7B.

The comparison circuit 7B receives the count value DCHTN input from the counter circuit 7A and the second reference value data DII! set in the second register circuit 10! F! The vertical synchronization period detection signal Sv is sent to the continuous detection circuit 5, which rises during a period from the start of counting until the count value DC, . . . is equal to the second reference value data I)tt□.

Here, as the second reference value data D□, a count value D CWT□ corresponding to the vertical synchronization period is selected, and thereby the vertical synchronization period from the beginning of the vertical synchronization pulse detection signal S vsI is detected.

Here, the continuity detection circuit 5 has a gate circuit configuration, and gates the vertical synchronization pulse detection signal Svs+ in response to the rise of the vertical synchronization period detection signal Sv, and sends it to the subsequent vertical synchronization signal detection circuit 11.

The vertical synchronization signal detection circuit 11 consists of a counter circuit 11A and a comparison circuit 11B, and the vertical synchronization pulse detection signal Svs+ gated by the continuous detection circuit 5 is input to the counter circuit 11A, so that the counter circuit 11A receives the vertical synchronization pulse detection signal svs+, and this count value D
CN? 3 is sent to the following comparison circuit 11B.

The comparison circuit 11B compares the count value DCHT3 inputted from the counter circuit 11A with the third reference value data D, E, set in the third register circuit 12, and the count value DcNts is the first value from the start of counting. A vertical synchronizing signal detection pulse vsyNc that rises for a predetermined period at a timing equal to the reference value data D□ of No. 3 is sent to the selector circuit 13.

Here, the third reference value data DI! F3 is selected to correspond to the number of vertical synchronization pulses PvsO included in the vertical synchronization period, and thereby the vertical synchronization signal V! It is designed to be able to detect YNe.

In addition to the vertical synchronization signal pulse pvs, the television signal VD sent from the clock synchronization circuit 2 is input to this selector circuit 13, and by the selector control signal C3□ input from the value "0" detection circuit 14, Vertical synchronization signal detection pulse V 3YNC or television signal VD,
Either one of them is sent to the outside as an output of the vertical synchronization separation circuit 1.

In the case of this vertical synchronization separation circuit 1, the first register circuit 4
The first reference value data D□ is set to .

is input to the value "0" detection circuit 14 in addition to the comparison circuit 3B of the vertical synchronization pulse detection circuit 3, and the value "0" detection circuit 14 detects that the first reference value data D is the value "0". When something is detected, a selector control signal C3□ is sent to the selector circuit 13 to output the television signal VD.

Here, in the frame window count circuit 9 of the framing processing circuit 8 attached to the vertical synchronization separation circuit 1, the vertical synchronization pulse latch signal Rvs inputted from the first latch circuit 6 is inverted and inputted to the clear input terminal. ing.

As a result, the frame window count circuit 9 counts the clock signal S0 from the timing of the first vertical synchronization pulse detection signal 5w5t, and this count value is N, 4.
is sent to the subsequent frame window leading edge comparison circuit 15 and frame window trailing edge comparison circuit 16.

The frame window leading edge comparison circuit 15 contains fourth reference value data D set in the fourth register circuit 17.
As a result, a window leading edge detection signal SwF is sent to the framing detection circuit 19, in which the count value DeN,4 rises at a timing that coincides with the fourth reference value data D, .

Further, the frame window trailing edge comparison circuit 16 receives fifth reference value data D set in the fifth register circuit 18.
IIK□ is input, which causes the count value DCNT4
sends to the framing detection circuit 19 a window trailing edge detection signal s1 that rises at a timing that coincides with the fifth reference value data I) mars.

Note that the window trailing edge detection signal SWm is inputted to the clear input terminal of the first latch circuit 6 and the vertical synchronization signal detection circuit 11 in addition to the framing detection circuit 19, whereby the window trailing edge detection signal SWm is input.

The detection operation of the vertical synchronization signal ends at the timing when the signal rises.

Here, in addition to the window leading edge detection signal SWF and the window trailing edge detection signal SWI, the television signal DI sent from the clock synchronization circuit 2 is input to the framing detection circuit 19.

As a result, the framing detection circuit 19 detects that the first horizontal synchronization pulse PM3 for one field following the vertical synchronization period is
Framing detection that indicates whether the following one field is an odd field or an even field depending on whether or not it exists between the rising edge of the window leading edge detection signal S@F and the rising edge of the window trailing edge detection signal seim. A signal 5FII is generated and sent to the second latch circuit 20.

This second latch circuit 20 has a vertical synchronization signal detection pulse V
A latch operation is executed at the timing when S'tHC rises, and the latched framing detection signal S
F□ is sent out as the output of the framing processing circuit 8.

Incidentally, when the power is turned on, each register circuit 4, 10, 12, 17, and 18 of the vertical synchronization separation circuit 1 and the framing processing circuit 8 in this embodiment receives the television signal SVO by the vertical synchronization separation control circuit 21 shown in FIG. Reference value data DateIs DlllLWZs, respectively corresponding to
D*tvss DI! F4s DI giant FS is set.

That is, this vertical synchronization separation control circuit 21 has a central processing unit (CPU) 22, and an address bus 23 and a data bus 24 derived from this CPU 22 are connected to a ROM (rea
d only memory) 25 is connected.

Further, an address decoder 26 is connected to the address bus 23, and when address designation data for each register circuit 4, 10, 12, 17 and 18 is input, it is decoded and sent to the first to fifth AND gate circuits 27A. ~27E
Send to.

The first to fifth AND gate circuits 27A to 27E have CP
A write command is input from U22 through the write line 28, and thus the write commands W, W, Wc% are sequentially sent to each register circuit 4, 10, 12, 17 and 18.
We-, Wt are input.

This allows each register circuit 4.10.12.17 and 1
8 includes write commands Wa, We, Wc, Wwa, W
The contents of the data bus 24 are written at a timing corresponding to o.

In practice, the ROM 25 contains vertical synchronization separation circuit constant data, as shown in FIG. The number Ct and the number C1 of falling periods of the vertical synchronization pulse pvs are stored.

In addition to this, the vertical synchronization separation circuit constant data includes the count numbers 04 and C1 to the leading and trailing edges of the window for detecting the first horizontal synchronizing pulse pws of an even field following the vertical synchronizing period, for example. The information is stored so that framing detection processing can be executed.

In this way, in the case of the vertical synchronization separation circuit 1 according to this embodiment, the television signal Sv! is stored in the ROM 25! Vertical synchronization separation circuit constant data c1, Cz, Cx, C according to l
4. By setting and storing Cs in advance, the constants necessary for the vertical synchronization separation circuit 1 are set when the power is turned on, and the television signal is NTSC as shown in Figures 6 (A) to (C).
A vertical synchronization signal can also be detected in the case of C television system and PAL television system.

Furthermore, if a clock signal having a frequency that is a predetermined times higher than the clock signal S0 is given, the vertical synchronization signal can also be used when the television signal is of the high-definition television system shown in FIG. 6(D), as described above. can be detected.

According to the above configuration, by setting and storing the vertical synchronization separation circuit constant data according to the television signal Sv in advance, the necessary constants are set when the power is turned on, and the vertical synchronization signal of the desired television signal is detected. It is possible to realize a digital vertical synchronization separation circuit that can perform

Furthermore, if such a vertical synchronization separation circuit is integrated into a single chip, it will be possible to support various television systems by simply setting the vertical synchronization separation circuit constant data externally, thereby further improving the versatility of the vertical synchronization separation circuit. A separate circuit can be realized.

In the above-described embodiment, a case has been described in which vertical synchronization separation circuit constant data corresponding to a desired television signal is stored in the ROM, but instead of this, vertical synchronization separation circuit constant data corresponding to a plurality of television signals is stored. The circuit constant data may be stored in a ROM, and the vertical synchronization separation circuit constant data corresponding to a desired television signal may be read out by a command set from the outside.

In the above embodiments, the case where the television system is compatible with the NTSC television system, the PAL television system, or the high-definition television system has been described, but the invention is not limited to this, and it can also be applied to X-ray VTRs, simple television systems, etc. Vertical synchronization signals can be detected in the same way as in the above-described embodiments even in the case of various television signals on the ground.

H Effects of the Invention As described above, according to the present invention, the first, second and third count values are set according to the desired television signal, and the clock is set according to the synchronization pulse included in the television signal. A vertical synchronization pulse is detected by counting up to a first count value, and a vertical synchronization period is detected by counting from the timing of the first vertical synchronization pulse to a second count value, and during this vertical synchronization period, a vertical synchronization pulse is detected. By counting up to the third count value, the versatility can be greatly improved, and the vertical synchronization signal of various television signals can be detected with a relatively simple circuit configuration and high separation timing accuracy. It is possible to realize a vertical synchronization separation circuit that can perform

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the vertical synchronization separation circuit according to the present invention, FIG. 2 is a block diagram showing its control circuit, and FIG. 3 provides an explanation of constant data set in the vertical synchronization separation circuit. Figure 4 is a signal waveform diagram showing the operation of an analog type vertical synchronization separation circuit, Figure 5 is a signal waveform diagram showing the operation of a digital type vertical synchronization separation circuit, and Figure 6 is a signal waveform diagram showing the operation of a digital type vertical synchronization separation circuit. FIG. 3 is a signal waveform diagram showing a vertical synchronization period. 1...Vertical synchronization separation circuit, 3...Vertical synchronization pulse detection circuit, 4.10.12.17.18...
. . . Register circuit, 7 . . . Vertical synchronization period detection circuit, 8 . . . Framing processing circuit, 11.
...Vertical synchronization signal detection circuit.

Claims (1)

[Claims] In accordance with a desired television signal, a first count value corresponding to a period longer than a horizontal synchronization pulse and shorter than a vertical synchronization pulse of the television signal; count value setting means for setting a second count value corresponding to the number of vertical synchronization pulses included in the vertical synchronization period and a third count value corresponding to the number of vertical synchronization pulses included in the vertical synchronization period; From the timing when the front edge of the vertical sync pulse is detected, a clock having a shorter period than the horizontal sync pulse is counted up to the first count value and a vertical sync pulse detection signal is sent, or the trailing edge of the horizontal sync pulse is a first counting means for resetting at the detected timing; and a second counting means for detecting the vertical synchronization period by counting a predetermined clock from the timing of the first vertical synchronization pulse detection signal up to a second count value. and third counting means for counting the vertical synchronization pulse detection signal up to the third count value during the vertical synchronization period to detect the vertical synchronization signal of the television signal. Vertical sync separation circuit.