JPH04360574A - Semiconductor nonvolatile memory and its programming method - Google Patents

Abstract

PURPOSE:To erase only data of a memory cell at the intersection of a selected word line and a bit line for programming without making any peripheral circuit complicated by separating wells from each other at every bit line used for making one-time erasure or writing and constituting the memory cell of a plurality of wells. CONSTITUTION:When, for example, memory cells 13 are arranged in a matrix- like state at intersections of word lines 11 and bit lines 15, the wells constituting the memory cells 13 are respectively separated to, for example, two wells, the first well 17a and second well 17b, at every bit line 15 for preparing a one-time erase or write program. In the first and second wells 17a and 17b, the memory cell to be connected to each bit line 15 for executing a program at once is formed. Therefore, even when an erasing or writing program is executed on the memory cell 13 connected to a selected word line 11 and bit line 15, other memory cells which are not used at the time of executing the program are not erased.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor nonvolatile memory and a programming method for erasing and writing.

0002

[Prior Art] A circuit diagram showing a memory cell in FIG. 3 and a circuit diagram in FIG.
A conventional semiconductor non-volatile memory will be explained using a circuit diagram showing a non-volatile memory.

One memory cell 13 constituting a semiconductor nonvolatile memory includes, for example, as shown in FIG. 3, a memory transistor 23 for storing information, an address transistor 21 for selecting a memory address, and a source It consists of an isolation transistor 25 for isolation from the potential. A plurality of memory cells 13 are arranged in a matrix to form a nonvolatile memory.

FIG. 2 shows the memory cell 13 shown in FIG.
1 is a circuit diagram for explaining the configuration of a conventional nonvolatile memory arranged in a matrix.

A memory cell 13 is arranged at each intersection between the word line 11 and the bit line 15.

All of the memory cells 13 are formed in a single well 17. The well 17 is a diffusion region formed in a semiconductor substrate, and is a diffusion region into which an impurity of the same conductivity type as the semiconductor substrate or an impurity of the opposite conductivity type is introduced.

In a conventional semiconductor nonvolatile memory, all memory cells 13 are formed in a single well 17, as shown in FIG. 2, in order to increase the degree of integration.

[0008] Also, on one side of all the bit lines 15,
A data latch circuit 19 is arranged.

[0009]

[Problems to be Solved by the Invention] When performing a program for erasing and writing each memory cell 13 in the above-described nonvolatile memory configuration, it is necessary to
must be programmed each time. That is, first one word line 11 is selected, then one bit line 15 is selected, and a predetermined memory cell is programmed.

However, one selected word line 11
Some memory cells 13 are connected to bit lines 15 that are not programmed. Therefore, before erasing the data in all memory cells 13 connected to the selected word line 11, the data latch circuit 19 connected to one of the bit lines 15 connecting each memory cell 13 is Transfer 13 data.

After the data of the memory cell 13 has been transferred to the data latch circuit 19, the gate potential of the memory transistor 23 of all the memory cells 13 connected to the word line 11 is set to a high potential, as shown in FIG. do. As a result, data in all memory cells 13 connected to the selected word line 11 is erased.

Thereafter, the memory cell 13 to be written receives data from the bit line 15 and rewrites the contents of the data latch circuit 19. On the other hand, data is written into the memory cell 13 that is not to be written using the data transferred to the data latch circuit 19 before erasing.

In the semiconductor nonvolatile memory configuration described above, even the memory cells 13 that are not programmed are erased. Therefore, the data latch circuit 1 that transfers the data of the memory cell before erasing the data of the memory cell
A peripheral circuit such as 9 is required to be provided around the memory cell 13. Therefore, the configuration of this peripheral circuit becomes complicated, and the presence of this data latch circuit 19 increases the chip area of the semiconductor nonvolatile memory.

The present invention solves these conventional problems and erases only data in memory cells where a selected word line and a bit line to be programmed intersect, without complicating peripheral circuits. The purpose of the present invention is to provide a structure of a semiconductor nonvolatile memory that allows data to be erased and a programming method that performs erasing and writing.

[0015]

Means for Solving the Problems In order to achieve the above object, a semiconductor nonvolatile memory of the present invention employs the structure and method described below.

The structure of the semiconductor nonvolatile memory of the present invention is as follows:
In a semiconductor non-volatile memory in which a memory cell that has at least a memory transistor and is formed in a well is placed at the intersection of a word line and a bit line, this well is separated for each bit line that is erased or written at one time, and is divided into multiple wells. The wells that form memory cells are separated for each bit line unit that is erased and written at one time.

In the semiconductor nonvolatile memory programming method of the present invention, the gate potential of the memory transistor connected to the word line is set to a high potential, and the potential of the first well forming the bit line for erasing and writing is set to the substrate potential. Then, the potential of the second well where a bit line that is not to be erased or written is set to a high potential, the memory transistor formed in the first well is erased, and then information is written to the memory transistor of the first well. It is characterized by doing the following.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings. The circuit diagram of FIG. 1 showing the configuration of the semiconductor non-volatile memory of the present invention, the circuit diagram of FIG. 3 showing one memory cell of the semiconductor non-volatile memory, and the circuit diagram of FIG. 4 showing the structure of the semiconductor non-volatile memory of the present invention. This will be explained with reference to a sectional view.

As shown in FIG. 3, the memory cell 13 selects a memory address and selects an address transistor gate 31.
an N-channel address transistor 21 connected to;
Consists of an N-channel memory transistor 22 that stores information and is connected to a memory transistor gate 33, and an N-channel isolation transistor 25 that is connected to an isolation transistor gate 29 and is isolated from the source potential during programming. do. word line 1
1 consists of a memory transistor gate 33, an address transistor gate 31, and an isolation transistor gate 29. This memory cell 13 is arranged at the intersection of each word line 11 and each bit line 15.

The memory cell 13 may have any configuration as long as it includes at least the memory transistor 23. That is, the isolation transistor 25 and the address transistor 21 may be omitted. Furthermore, the memory transistor 23 may be a floating gate structure type memory, an MNOS structure type memory, or a MONOS structure type memory in which an oxide film is formed on a silicon nitride film which is a gate insulating film of the MNOS structure type memory. It can be of any structure. Furthermore, the memory transistor 23
The conductivity type may be not only N-channel but also P-channel. However, when the memory transistor 23 is a P-channel, the address transistor 21 and the isolation transistor 25 are P-channel, same as the memory transistor 23. Therefore, the well forming the memory cell 13 becomes an N well.

The memory cell 13 explained using FIG.
When arranged at the intersections of word lines 11 and bit lines 15 and arranged in a matrix, in the present invention, as shown in FIG. Every bit line 15 performs
For example, it is separated into two wells, a first well 17a and a second well 17b. Here, the first well 17a
If the memory transistor 23 is an N channel, the conductivity type of the second well 17b is P type.

Memory cells 13 connected to bit lines 15 corresponding to the number of bits to be programmed at one time are formed in each of the first well 17a and second well 17b. Each of the first well 17a and the second well 17b has a number of bit lines to be programmed at one time, for example 512 bit lines.
It is formed separately in units of bits and 4K bits.

Note that in the nonvolatile memory shown in FIG. 1, the first well 1 is
Although only two wells, 7a and second well 17b, are shown, if the memory capacity increases, two or more separate wells may be formed.

Next, the operation of the circuit based on the above configuration will be explained using FIG. When performing erasing and writing programs on the memory cells 13 connected to a selected word line 11 and a selected bit line 15, the following method is used.

The potential of the memory transistor gates 33 of all the memory cells 13 shown in FIG. 3 connected to the selected word line 11 is set to a high potential. The well of the bit line 15 to be further programmed, for example the first well 1
Let the potential of 7a be the potential of the substrate 41 in the cross-sectional view of the semiconductor nonvolatile memory in FIG. Furthermore, the potential of the well of the bit line 15 that is not to be programmed, for example, the second P well 17b, is set to the memory transistor gate 3.
Set it to the same high potential as in 3.

As a result, the data in the memory transistor 23 of the memory cell 13 formed in the first well 17a and connected to the selected word line 11 is transferred to the memory transistor gate 33 shown in FIG. The data is erased by the potential between the bulk 37, that is, the high potential between the memory transistor gate 33 and the first well 17a.

On the other hand, formed in the second well 17b,
Memory cell 13 connected to the selected word line 11
The data in the memory transistor 23 is not erased because the potential between the memory transistor gate 33 and the memory transistor bulk 37 is the same.

When writing data, all the memory transistor gates 33 of the memory cells 13 shown in FIG. 3 connected to the selected word line 11 are
The potential of is set to the substrate 41 potential shown in FIG.
The well of the bit line 15 to be written, for example, the first well 17a, is set to a high potential. On the other hand, the second well 17b to which writing is not performed may be at the same high potential as the first well 17a or at the substrate 41 potential.

The potential of the bit line 15 connected to the memory cell 13 to be written is set to the first well 17a.
It is possible to write data into the memory cell 13 by setting it to the same high potential as . For memory cells 13 to which no writing is to be performed, writing is not performed by setting the bit line 15 connected to the memory cell 13 to the potential of the substrate 41 shown in FIG.

[0030]

As described above, according to the present invention, it is possible to erase only the data in the memory cells where the selected word line intersects with the bit line to be programmed. Furthermore, the data latch circuit that was conventionally required is no longer necessary, which has the effect of simplifying the peripheral circuitry of the semiconductor nonvolatile memory compared to the conventional one, and making it possible to reduce the chip area of the semiconductor nonvolatile memory.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the structure of a semiconductor nonvolatile memory according to the present invention.

FIG. 2 is a circuit diagram showing the structure of a conventional semiconductor nonvolatile memory.

FIG. 3 is a circuit diagram showing the structure of a memory cell in the present invention and a conventional example.

FIG. 4 is a cross-sectional view showing the structure of the semiconductor nonvolatile memory of the present invention.

[Explanation of symbols]

11 Word line 13 Memory cell 15 Bit line 17a First well 17b Second well 19 Data latch circuit 23 Memory transistor 41 Substrate

Claims (2)

[Claims] 1. A semiconductor non-volatile memory in which a memory cell having at least a memory transistor and formed in a well is arranged at the intersection of a word line and a bit line, wherein the well is connected to the bit line which is erased and written at one time. A semiconductor non-volatile memory characterized by being separated from each other and consisting of multiple wells. 2. The potential of the gate of the memory transistor connected to the word line is set to a high potential, the potential of the first well forming the bit line to be erased or written is set to the substrate potential, and the bit is not erased or written. The memory transistor formed in the first well is erased by setting the potential of the second well in which the line is formed to a high potential, and then information is written to the memory transistor in the first well. A method of programming semiconductor non-volatile memory.