JPH0436112Y2 - - Google Patents

Info

Publication number
JPH0436112Y2
JPH0436112Y2 JP1986052405U JP5240586U JPH0436112Y2 JP H0436112 Y2 JPH0436112 Y2 JP H0436112Y2 JP 1986052405 U JP1986052405 U JP 1986052405U JP 5240586 U JP5240586 U JP 5240586U JP H0436112 Y2 JPH0436112 Y2 JP H0436112Y2
Authority
JP
Japan
Prior art keywords
metal film
fet
package
effect transistor
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1986052405U
Other languages
Japanese (ja)
Other versions
JPS62163944U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986052405U priority Critical patent/JPH0436112Y2/ja
Publication of JPS62163944U publication Critical patent/JPS62163944U/ja
Application granted granted Critical
Publication of JPH0436112Y2 publication Critical patent/JPH0436112Y2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Amplifiers (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は半導体装置に関し、特に高周波領域で
使用される電界効果トランジスタ（以下FETと
いう）の内部整合回路に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, and particularly to an internal matching circuit of a field effect transistor (hereinafter referred to as FET) used in a high frequency region.

〔従来の技術〕[Conventional technology]

従来、高周波用のFETに用いられる出力用整
合回路は、FETの外に集中定数あるいはマイク
ロストリツプラインとして、パツケージ出力端子
と出力伝送路との間に接続されるのが一般的であ
つた。 Conventionally, output matching circuits used in high-frequency FETs have generally been connected outside the FET as lumped constants or microstrip lines between the package output terminal and the output transmission line.

〔考案が解決しようとする問題点〕[Problem that the invention attempts to solve]

一般に高周波用FETのパツケージ出力端子か
ら見た出力インピーダンスは伝送線路の特性イン
ピーダンスに対して小さい為、整合回路により大
きなインピーダンスに変換を行う必要がある。こ
のため、特に高帯域アンプを実現する上では多く
の回路部品を必要とする。 Generally, the output impedance seen from the package output terminal of a high-frequency FET is smaller than the characteristic impedance of the transmission line, so it is necessary to convert it to a larger impedance using a matching circuit. For this reason, a large number of circuit components are required, especially when realizing a high-bandwidth amplifier.

又、高周波用FETのソース電極とパツケージ
のソース端子間は、高周波動作用に底インダクタ
ンス化のため、多数本のボンデイングワイヤーで
接続する必要があるが、高周波用FETのソース
電極面積はその構造上限られる為、低インダクタ
ンス化に十分な多数本のボンデイングワイヤーを
接続することが不可能であつた。更に高密度にボ
ンデイングを行う為、製造上の歩留低下の原因と
なつていた。 In addition, the source electrode of the high-frequency FET and the source terminal of the package must be connected using multiple bonding wires to create a bottom inductance for high-frequency operation, but the area of the source electrode of the high-frequency FET is at the upper limit of its structure. Therefore, it has been impossible to connect a sufficient number of bonding wires to reduce the inductance. Furthermore, bonding is performed at a high density, which causes a decrease in manufacturing yield.

〔問題点を解決するための手段〕[Means for solving problems]

本考案では出力整合回路の第１段目の並列接続
容量を、半導体基板、酸化膜及び金属膜による
MOS容量としてFETと同一基板内に形成してい
る。 In this invention, the parallel connection capacitance of the first stage of the output matching circuit is formed by a semiconductor substrate, an oxide film, and a metal film.
It is formed on the same substrate as the FET as a MOS capacitor.

本考案の半導体装置は、電界効果トランジスタ
と、この電界効果トランジスタと同一半導体基板
上に形成された酸化膜と金属膜とからなるMOS
容量とを有し、電界効果トランジスタのソース電
極が金属膜に接続され、金属膜とパツケージの端
子とがボンデイングワイヤーで接続されたことを
特徴とする。 The semiconductor device of the present invention consists of a field effect transistor and an oxide film and a metal film formed on the same semiconductor substrate as the field effect transistor.
The source electrode of the field effect transistor is connected to a metal film, and the metal film and the terminal of the package are connected with a bonding wire.

〔実施例〕〔Example〕

次に本考案について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図ａ及び第１図ｂは本考案の一実施例の平
面図及び断面図である。ドレインとなる半導体基
板８の表面上に形成された酸化膜４と金属膜１お
よび半導体基板８とによりMOS容量を形成して
いる。金属膜１はソース電極２として直接FET
上に延びバツクゲート領域６内に形成されたソー
ス拡散層５と接続している。ゲート電極３が酸化
膜上に設けられており、半導体基板８の裏面には
ドレイン電極７が設けられている。 FIGS. 1a and 1b are a plan view and a sectional view of an embodiment of the present invention. A MOS capacitor is formed by the oxide film 4 formed on the surface of the semiconductor substrate 8, which serves as a drain, the metal film 1, and the semiconductor substrate 8. Metal film 1 is directly connected to FET as source electrode 2
It extends upward and is connected to the source diffusion layer 5 formed in the back gate region 6. A gate electrode 3 is provided on the oxide film, and a drain electrode 7 is provided on the back surface of the semiconductor substrate 8.

第２図は、パツケージ実装時の一実施例であ
る。FETのソースに接続した金属膜１は、ボン
デイングワイヤ１１により、パツケージ９のソー
ス端子１０に接続され、裏面電極７はパツケージ
のドレイン端子１２に接続されている。 FIG. 2 shows an example of mounting the package. The metal film 1 connected to the source of the FET is connected to the source terminal 10 of the package 9 by a bonding wire 11, and the back electrode 7 is connected to the drain terminal 12 of the package.

第３図は本考案の一実施例のFETを実装した
回路実施例の等価回路であり、破線１３で囲んだ
部分がMOS容量２０を同一基板上に有するFET
２１とからなる本考案の一実施例の等価回路であ
る。 FIG. 3 is an equivalent circuit of a circuit example in which an FET according to an embodiment of the present invention is mounted.
21 is an equivalent circuit of an embodiment of the present invention.

従来、パツケージ外部に接続された第１段目並
列容量がFETと同一基板上に形成されているこ
とを示す。 Conventionally, the first stage parallel capacitor connected to the outside of the package is formed on the same substrate as the FET.

〔考案の効果〕[Effect of idea]

以上説明したように本考案は、FETと同一基
板内にドレイン、ソース間と並列のMOS容量を
形成し、内部整合回路用並列容量とすることによ
り、広帯域アンプの設計を行う上で、外付け部品
点数の低減が可能となる。さらに、パツケージの
ソース電極との接続は、面積の広い内部整合回路
用のMOS容量金属膜を用いることが出来る為、
ボンデイングが容易となり歩留向上の効果があ
る。 As explained above, this invention forms a parallel MOS capacitor between the drain and source on the same substrate as the FET, and uses it as a parallel capacitor for the internal matching circuit. It is possible to reduce the number of parts. Furthermore, the connection with the source electrode of the package can be made using a MOS capacitor metal film for the internal matching circuit, which has a large area.
Bonding is facilitated, which has the effect of improving yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａは本考案の一実施例の平面図、第１図
ｂは第１図ａの断面図、第２図は本考案の一実施
例のFETのパツケージ実装時の側面図、第３図
は本考案の一実施例のFETの回路実装例の等価
回路図である。 １……金属膜、２……ソース電極、３……ゲー
ト電極、４……酸化膜、５……ソース拡散層、６
……バツクゲート領域、７……ドレイン電極、８
……半導体基板、９……パツケージ、１０……パ
ツケージのソース端子、１１……ボンデイングワ
イヤー、１２……パツケージのドレイン端子、１
３……本考案の一実施例のMOS容量を有する
FETの等価回路、１４……整合回路入力端子、
１５……整合回路出力端子、１６……ゲート直流
バイアス回路、１７……直流バイアス回路、１８
……整合用インダクタンス、１９……整合用容
量、２０……FETと同一基板上に形成したMOS
容量、２１……FET。 Figure 1a is a plan view of an embodiment of the present invention, Figure 1b is a sectional view of Figure 1a, Figure 2 is a side view of an embodiment of the present invention when the FET is mounted on a package, The figure is an equivalent circuit diagram of an example of circuit implementation of an FET according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Metal film, 2... Source electrode, 3... Gate electrode, 4... Oxide film, 5... Source diffusion layer, 6
... Back gate region, 7 ... Drain electrode, 8
...Semiconductor substrate, 9...Package, 10...Source terminal of package, 11...Bonding wire, 12...Drain terminal of package, 1
3...has the MOS capacity of an embodiment of the present invention
FET equivalent circuit, 14... matching circuit input terminal,
15... Matching circuit output terminal, 16... Gate DC bias circuit, 17... DC bias circuit, 18
...Matching inductance, 19...Matching capacitor, 20...MOS formed on the same substrate as FET
Capacity, 21...FET.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電界効果トランジスタと、該電界効果トランジ
スタと同一半導体基板上に形成された酸化膜と金
属膜とからなるMOS容量とを有し、前記電界効
果トランジスタのソース電極が前記金属膜に接続
され、該金属膜とパツケージの端子とがボンデイ
ングワイヤーで接続されたことを特徴とする半導
体装置。 It has a field effect transistor and a MOS capacitor formed of an oxide film and a metal film formed on the same semiconductor substrate as the field effect transistor, the source electrode of the field effect transistor is connected to the metal film, and the metal film is connected to the metal film. A semiconductor device characterized in that a film and a terminal of a package are connected with a bonding wire.
JP1986052405U 1986-04-07 1986-04-07 Expired JPH0436112Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986052405U JPH0436112Y2 (en) 1986-04-07 1986-04-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986052405U JPH0436112Y2 (en) 1986-04-07 1986-04-07

Publications (2)

Publication Number Publication Date
JPS62163944U JPS62163944U (en) 1987-10-17
JPH0436112Y2 true JPH0436112Y2 (en) 1992-08-26

Family

ID=30877546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986052405U Expired JPH0436112Y2 (en) 1986-04-07 1986-04-07

Country Status (1)

Country Link
JP (1) JPH0436112Y2 (en)

Also Published As

Publication number Publication date
JPS62163944U (en) 1987-10-17

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