JPH04361179A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To perform an electrical test in a state near to the operation frequency of an LSI within a short time. CONSTITUTION:The cascade connection part of an input buffer 1, a combination logical circuit 2, a memory circuit 3, a combination logical circuit 2a and an output buffer 4 is composed of the same circuit constitution as a conventional LSI and a testing clock signal generating part 20 is inserted between the clock input node N and clock input terminal T3 thereof. The testing clock signal generating part 20 has a selector 5 having the clock input terminal T3 at its one input terminal and inputting the (1/n) clock signal S6 of a sub-clock signal S4 at its other terminal and changing over an internal output clock signal S7 by a test mode signal S5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a circuit for testing the operation of internal logic circuits using a logic tester.

0002

[Prior Art] Recently, semiconductor integrated circuit devices (hereinafter referred to as LSI)
), the types of circuits are becoming more diverse, and the number of circuits housed in LSIs is also increasing. Also, a few years ago, the number of circuits housed was in the tens of thousands of gates,
In the near future, it is likely to be put into practical use as a circuit scale of hundreds of thousands to millions of gates.

As the number of circuits housed in an LSI increases, the chip size of the LSI increases, and the operating performance required of the LSI increases, leading to an increase in the operating frequency.

[0004] When testing a conventional LSI consisting of blocks as shown in FIG. clock signal S
3, the LSI is activated and tested by comparing its output signal S2 with the expected value using an external comparison circuit.

Next, the operation of the LSI will be explained in more detail. Input data S1 is input to input buffer 1, and the output of input buffer 1 is sent via data line 8 to an AND circuit, N
The signal is sent to a combinational logic circuit 2 consisting of a combinational circuit consisting of an AND circuit, an OR circuit, etc., and a register, etc. The output signal of the combinational logic circuit 2 is connected to R via the data line 9.
The signal is input to a memory circuit 3 composed of an AM or the like, and the output of the memory circuit 3 is further sent to a combinational logic circuit 2a via a data line 10. The output signal of the combinational logic circuit 2a is input to the output buffer 4 via the data line 11, and the output signal of the output buffer 4 is further output to the outside of the LSI as output data S2.

On the other hand, when the memory circuit 3 is separated from the combinational logic circuit 2 and the combinational logic circuit 2a and the memory circuit 3 is electrically tested, the paths of the data lines 12 and 13 are used.

[0007]

[Problem to be Solved by the Invention] In testing the logic characteristics of this conventional LSI, the frequency of the clock signal applied to the LSI from an external logic tester to confirm the operation of the LSI is different from the actual operating frequency of the LSI. The situation is becoming far different in comparison.

For example, the operating frequency of a logic tester is several M.
Hz, but the actual operating frequency of the LSI is 20 to 100 MHz.
If it is far from z, there is a problem that it is not possible to test the performance at high speed when the LSI actually operates.

[0009]

[Means for Solving the Problems] The LSI of the present invention is capable of testing the logic operation of an internal circuit including a combinational logic circuit or a memory circuit that inputs a clock signal from a clock terminal through a clock input node. In a semiconductor integrated circuit that inputs test input data from a logic tester to the internal circuit and outputs test output data, a sub-clock signal synchronized with the clock signal and a test signal are provided between the clock terminal and the clock input node. A test clock having a clock (1/n) frequency dividing circuit that inputs a mode signal to two input terminals and supplies an internal clock signal with a period (1/n) of the clock signal from the output terminal to the clock input node. It is constructed by inserting a signal generator.

0010

Embodiments Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a time chart of clock signals for explaining the operation of the blocks in FIG.

In FIG. 1, the cascade connection part of the LSI input buffer 1, combinational logic circuit 2, memory circuit 3, combinational logic circuit 2a, and output buffer 4 has the same circuit configuration as the conventional LSI shown in FIG. A test clock signal generator 20 is inserted between the clock input node N and the clock input terminal T3. The test clock signal generator 20 has one input terminal connected to the clock input terminal T3,
The other input terminal inputs a (1/n) clock signal S6 of the sub-clock signal S4, and has a selector 5 which switches the internal output clock signal S7 in accordance with the test mode signal S5.

The operation of the cascade connection from the input buffer 1 to the output buffer 4 is similar to the operation of the block in FIG. 3 described in the prior art section.

Combinational logic circuit 2 from clock input node N
, 2a and the internal clock signal S supplied to the memory circuit 3.
7, the logic of the test mode signal S5 is “0” or “
1'', either the main clock signal S3 or the (1/n) clock signal S6 output from the clock (1/n) frequency dividing circuit 6 is selected.

Furthermore, the test mode signal S5 is logic "1".
Only in this case, the clock (1/n) frequency dividing circuit 6 operates,
As shown in FIG. 2, (1/1
A (1/n) clock signal S6 having a clock period T2 divided by 0) is output from the clock (1/n) frequency dividing circuit 6.

Next, electrical testing of LSI will be explained in detail with reference to FIGS. 1 and 2. First, the clock applied to the LSI from the tester for testing the LSI is divided into (1/2) of the basic clock of the tester, and the clock signal is used as the sub-clock signal S4 of the LSI to clock the test clock signal generator 20. It is input to the 1/n frequency divider circuit 6.

Next, the test mode signal S5 is set to logic "1", the clock (1/n) frequency dividing circuit 6 is activated, and the sub clock signal S4 is divided into (1/10). n)
A clock signal S6 is supplied via a clock input node N to the respective clock ends of the combinational logic circuits 2, 2a and the memory circuit 3.

[0017] There is also a scan path method and a test method in which a specific value (“0” or “1”) is set to LSI input data that has been simulated in advance to effectively activate the logic circuit of the LSI. Conduct an electrical test using both.

In this embodiment, the clock period on the tester side is T.
1.The clock cycle on the LSI side is different from T2, but the LSI
The T1 and T2 are synchronized in advance according to the number of logic stages and logic configuration within the LSI, and an external comparison circuit compares the output data S2 of the LSI with the expected value obtained by simulation in advance. can be tested at a frequency 20 times higher than the tester's clock, which is close to the actual operating clock.

[0019]

Effects of the Invention As explained above, the present invention incorporates a clock frequency dividing circuit into an LSI, and operates only when the LSI is set to the test mode.
This has the advantage that electrical tests can be performed in a short time at a state close to the operating frequency of the LSI required for I.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a time chart of clock signals for explaining the operation of the blocks in FIG. 1;

FIG. 3 is a block diagram of an example of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

1 Input buffers 2, 2a Combinational logic circuit 3 Memory circuit 4 Output buffer 5 Selector 6 Clock (1/n) frequency dividing circuits 8 to 13
Data line S1 Input data S2 Output data S3 Main clock signal S4 Sub-clock signal S5 Test mode signal S6 (1/n) clock signal S7 Clock signal

Claims (1)

[Claims] 1. When testing the logical operation of an internal circuit including a combinational logic circuit or a memory circuit that inputs a clock signal from a clock terminal through a clock input node,
In a semiconductor integrated circuit that inputs test input data from an external logic tester to the internal circuit and outputs test output data, a sub-clock signal synchronized with the clock signal is provided between the clock terminal and the clock input node. and test mode signals are input to two input terminals, and the clock signal (1) is input from the output terminal to the clock input node.
/n) clock supplying an internal clock signal with period (1
/n) A semiconductor integrated circuit device, characterized in that a test clock signal generation section having a frequency dividing circuit is inserted.