JPH043615A - D latch circuit - Google Patents

Abstract

PURPOSE:To considerably shorten the delay time until latch output data is changed and to increase the operation speed by performing the selective operation of a multiplexer only with a strobe signal and directly supplying a clock signal to a dynamic holding circuit in the output stage to perform the latch operation. CONSTITUTION:This circuit is provided with a multiplexer 3 which selects and outputs one or plural input data by the strobe signal and takes latch output data as the feedback input and a dynamic holding circuit 4 which dynamically holds the output of the multiplexer 3 in accordance with the clock signal and outputs it as latch output data. Since this holding operation is performed by the supply of the clock signal to the dynamic holding circuit 4 nearest to an output terminal 6, the number of gates interposed between the output of the clock signal and the change of latch output data is reduced to shorten the delay time till latch output. Thus, the operation speed of the circuit is considerably improved.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is applicable to digital LSIs such as microcomputers.
The present invention relates to a clock-synchronized D latch circuit used inside a device, and particularly to a D latch circuit suitable for a high-speed operation circuit constituted by MO8I transistors.

[Prior Art] Conventionally, as this type of clock synchronous D latch circuit,
A circuit is known that performs a data holding operation by feeding back the output of a multiplexer.

FIG. 7 is a circuit diagram showing an example of such a latch circuit. In order to simplify the explanation, an example will be described in which data is selected using one strobe signal S for one input data D.

In FIG. 7, input data D is input to multiplexer 61 via data input terminal 1. In FIG. Further, the strobe signal S and the clock signal CLK are connected to the NAND input terminal via the strobe input terminal 2 and the clock input terminal 5, respectively.
It is input to the gate 62, and this NAND gate 62
The output of the multiplexer 61 is supplied as a signal for determining its latch timing. The output of the multiplexer 61 is output as latch output data Q from the output terminal 6 via the inverter 63.

Further, this latch output data Q is sent to the multiplexer 61
has been returned to.

The multiplexer 61 is configured by cascading a transfer gate 64 and an inverter 65 between its input end and output end. Furthermore, the latch output data Q fed back into the multiplexer 61 is transferred to the transfer gate 6
It is wired-ORed to the input end of the inverter 65 via the inverter 7. Transfer gates 64 and 67 are NAND
The conduction is selectively controlled by the output of the gate 62 and the output obtained by inverting this by the inverter 66.

Next, the operation of the D latch circuit configured as described above will be explained.

FIG. 8 is a timing diagram showing the operation of this D latch circuit.

As shown in this figure, normally when using this type of D latch circuit, the strobe signal S is the clock signal C.
It is changed while LK is at a low potential.

FIG. 8(a) is a timing diagram when the input data D is changed while the clock signal CLK is at a low potential. While the clock signal CLK is at a low potential, the input data D
is determined and the strobe signal S is set to a high potential.
Transfer gate 64 becomes conductive at the next rise of clock signal CLK, so input data D is transferred to transfer gate 64 and inverter 65. It is propagated to the output terminal 6 as latch output data Q via t33.

When the clock signal CLK falls, the transfer gate 64 becomes non-conductive and the transfer gate 67 becomes non-conductive.
is conductive, the latch output data Q is transferred to the inverter 6.
It is fed back to the input terminal of 5 and holds its logical value. Also,
When the strobe signal S is kept at a low potential, the clock signal CL
Even if K rises, latch output data Q does not change.

Further, FIG. 8(b) is a timing diagram when the input data D is changed while the clock signal CLK is at a high potential. In this case, when input data D is changed while both clock signal CLK and strobe signal S are at high potential, the input data is immediately propagated to output terminal 6 via transfer gate 64 and inverter 65, 63. Ru.

Then, when the clock signal CLK falls, the logical value is held.

FIG. 9 is a diagram showing an example in which latch circuits are arranged at the front stage and the rear stage of the circuit shown in FIG. 7, respectively.

The D latch circuit 70 is similar to that shown in FIG. 7, and includes transfer gates 71 and 76 and inverters 72 and 7.
3.75 and NAND gate 74c, transfer gates 64 and 67, inverters 65 and 63.66, respectively
It corresponds to the AND gate 62.

A latch circuit 51 is connected between the data input terminal 1 and the data input terminal of the D latch circuit 70. This latch circuit 51 includes cascade-connected inverters 53 and 55, and clock signals CLKI and -C inserted between them.
The transfer gate 54 has a dynamic holding function whose conduction is controlled by LKI.

Furthermore, a latch circuit 52 is connected between the output end of the D latch circuit 70 and the output terminal 6.

This latch circuit 52 includes an inverter 56 connected in cascade.
．． 58 and a clock signal CLK inserted between them.
The transfer gate 57 has a dynamic holding function whose conduction is controlled by I and -CLKI.

FIG. 10 is a timing diagram showing the operation of this circuit.

As shown in FIG. 10(a), this circuit uses a two-phase clock signal CLK1. It operates according to CLK2.

First, when the clock signal CLKI rises, the transfer gate 54 of the latch circuit 51 becomes conductive.
Input data D- input to data input terminal 1 is propagated to point A. Next, after the strobe signal S rises,
When the clock signal CLK2 rises, the D latch circuit 70
The data at point A is latched and output to point B. Then, since the transfer gate 57 becomes conductive at the subsequent rise of the clock signal CLKI, the data at point B is outputted from the output terminal 6 as latch output data Q via the latch circuit 52.

[Problems to be Solved by the Invention] However, the above-described conventional D latch circuit has the following problems.

That is, in the circuit of FIG. 7, when the clock signal CLK rises during the active period of the strobe signal S, the output states of the NAND gate 62, the inverter 66, the transfer gate 64, and the inverters 65 and 63 sequentially change, and then the latch output is generated. Data Q changes. In other words, after the clock signal is input, the latch output changes while the signal propagates through the five stages of gates, so the time from the rise of the clock signal CLK to the change in the latch output data is long, which reduces the operating speed. There are problems that hinder improvement.

Further, in the circuit shown in FIG. 9, a delay time corresponding to two stages of gates caused by the NAND gate 74 and the inverter 75 occurs from the fall of the clock signal CLK2 until the transfer gate 71 is turned off. On the other hand, from the rise of the clock signal CLKI until the input data D is propagated to the point A, only a delay of one stage of gates caused by the inverter 55 occurs. Therefore, if the time from the fall of the clock signal CLK2 to the rise of the clock signal CLKI is shorter than the delay time of one stage of gates, the D latch circuit 70 will latch incorrect data. For this reason,
There is a problem in that the period during which both the clock signals CLKI and CLKI2 are at low potential cannot be made very short, and the operating speed cannot be improved.

The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a D latch circuit that can significantly improve operating speed.

[Means for Solving the Problems] A D latch circuit according to the present invention includes a multiplexer that selects and outputs one or more input data using a strobe signal, and to which latch output data is fed back, and an output of this multiplexer. The present invention is characterized by comprising a dynamic holding circuit that dynamically holds data according to a clock signal and outputs the latch output data.

[Operations] In the present invention, a multiplexer selects input data only by a strobe signal, and the data is held in a dynamic holding circuit provided on the output side of the multiplexer. This holding operation is performed by supplying the clock signal to the above-mentioned dynamic holding circuit closest to the output terminal, so it is possible to reduce the number of gates that intervene between the output of the clock signal and the change in latch output data. Delay time until output can be reduced.

Furthermore, in the present invention, since the holding operation in the dynamic holding circuit is performed immediately after inputting the clock signal, even when other latch circuits are placed before and after the D latch circuit of the present invention, the two-phase clock The period during which both are at low potential can be made sufficiently short.

Therefore, according to the present invention, the operating speed of the circuit can be significantly improved.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a D-laser circuit according to a first embodiment of the present invention.

This D latch circuit includes a multiplexer 3 that selects input data D input from a data input terminal 1 by a strobe signal S input from a strobe input terminal 2;
The dynamic holding circuit 4 holds the output of the multiplexer 3 according to the clock signal CLK input from the clock input terminal 5. The output of the dynamic holding circuit 4 is output from the output terminal 6 as latch output data Q, and is also fed back to the multiplexer 3.

FIG. 2 is a circuit diagram showing a more detailed configuration of the D latch circuit shown in FIG. 1.

The multiplexer 3 is configured as follows. That is, between the data input terminal 1 and the output terminal of the multiplexer 3, a transfer gate 11 and an inverter 12 are connected in cascade. Furthermore, the latch output data Q is wired-ORed to the input terminal of the inverter 12 via the transfer gate 14. These transfer gates 11 and 14 are selectively controlled to conduct by a strobe signal S input from the strobe input terminal 2 and a signal obtained by inverting this signal by an inverter 13.

The dynamic holding circuit 4 includes a transfer gate 15 and an inverter 16 connected in series between the output terminal of the multiplexer 3 and the output terminal 6. The transfer gate 15 has a dynamic holding function, and receives a clock signal CLK (positive phase) input from the clock input terminal 5a and the clock inversion input terminal 5b, respectively.
, -CLK (reverse phase) conduction is controlled. Note that the clock signal CLK is set so that its low potential time is shorter than the minimum time required for discharging dynamically held charges.

Next, the operation of the D latch circuit configured as described above will be explained.

Here, a case will be described in which the input data D1 strobe signal S and the clock signal CLK are input at the same timing as in FIG. 8(a). When the strobe signal S rises, the transfer gate 11 of the multiplexer 3 becomes conductive, so the selection operation of the multiplexer 3 is performed, and the input data D is transferred to the input terminal of the inverter 12.
The inverted output is output from the inverter 12.

Subsequently, when the clock signals CLK and -CLK become high potential and low potential, respectively, the transfer gate 15 of the dynamic holding circuit 4 becomes conductive, so that the latch output data Q is outputted to the output terminal 6 via the inverter 16.

Next, when the clock signals CLK and -CLK go to a low potential and a high potential, respectively, the transfer gate 15 becomes non-conductive, but its output level is maintained by the dynamic holding operation of the transfer gate 15.

Further, when the strobe signal S falls, the transfer gate 11 becomes non-conductive and the transfer gate 14 becomes conductive, so that the dynamic holding circuit 4
The latch output data Q held at is fed back to the input terminal of the inverter 12 via the transfer gate 14. As a result, during the low potential period of the strobe signal S,
Regardless of input data D, latch output data Q is held.

According to this circuit, the number of intervening gates from the rise of the clock signal CLK to the change of the latch output data Q is only two stages, transfer gate 15 and inverter 16, so the delay time corresponding to two stages of gates is required. It only arises. Therefore, the response time from the rise of the clock signal CLK until the latch output data Q changes can be reduced to 275 times compared to the conventional case.

FIG. 3 is a circuit diagram of a D latch circuit according to a second embodiment of the present invention.

In this embodiment, a clocked inverter 23.24 is used to configure the multiplexer 21 instead of the transfer gate 11.14 of the multiplexer 3 in the previous embodiment, and a clocked inverter 23.24 is also used instead of the transfer gate 15 of the dynamic holding circuit 4. This is an example in which the dynamic holding circuit 22 is configured using a clocked inverter 25 having a dynamic holding function, and the other configurations are the same as the circuit shown in FIG.

In this circuit as well, as in the circuit of the previous embodiment, the response time at the rise of the clock signal CLK can be shortened to the delay time of two stages of gates.

FIG. 4 is a circuit diagram of a D latch circuit according to a third embodiment of the present invention.

This embodiment is an example in which the present invention is applied to a D latch circuit that selectively latches a plurality of input data. That is, the multiplexer 31 has a data input terminal fat 1b+
Input data DO, Di, and D2 are input via the lcs, respectively. These input data Do-D2 are transferred to transfer gates 33a, 33b, 33, respectively.
It is supplied to the input end of the inverter 12 via c.

On the other hand, strobe signals So and Sl input from strobe input terminals 2b and 2a, respectively, are provided to a multiplexer control circuit 32. Multiplexer control circuit 32
is the strobe signal Sl.

Inverters 36a, 36b that invert SO, respectively, and four NAND gates 37a, 37b, 37 that receive all two combinations of the outputs of these inverters 36a, 36b and strobe signals si, so.
It consists of a decoder circuit with 37c and 37d.

NAND game of this multiplexer control circuit 32) 3
Each output of 7a, 37b, 37c, 37d is directly and inverter 35.34a, 34b,
The signals are supplied to the transfer gates 14 and 33 al 3 b + 33 c of the multiplexer 31 via the respective terminals 34 c, and their conduction states are selectively controlled.

The rest of the configuration is similar to the circuit shown in FIG.

The truth table for this D latch circuit is shown in Table 1 below. Note that here, H indicates a high potential, L indicates a low potential, and indicates a low potential or a high potential. Furthermore, the strobe signals so, si and input data DO to D2 are input at the same timing as the strobe signal S and input data D shown in FIG.

Table 1 According to this circuit, when the strobe signals S0 and 81 are both at low potential, the transfer gate 14 is conductive;
Transfer gates 33a to 33C become non-conductive,
The previous value is maintained. Strobe signal So, S
If both L are not at low potential, the transfer gates 33 a, 33 b,
33 c is conductive, transfer gate 14
becomes non-conductive, so one of the input data DO to D2 is selected and transferred to the input terminal of the inverter 12. Then, when the clock signal CLK rises, the data is held in the dynamic holding circuit 4.

FIG. 5 is a circuit diagram of a D latch circuit according to a fourth embodiment of the present invention.

In this embodiment, the multiplexer 41 is constituted by an AND-NOR composite gate 42 rather than a transfer gate. That is, the input data D input through the data input terminal 1 is input to one input terminal of the AND-NOR composite gate 42. Furthermore, the strobe signal S input from the strobe input terminal 2 is AND-N
It is input to the other input terminal of the OR composite gate 42, and
AND-NOR composite gate 42 via inverter 43
is input to yet another input terminal. And-
The latch output data Q is fed back to the other input terminal of the NOR composite gate 42 from the output side. and,
The output of this AND-NOR composite gate 42 is given to the dynamic holding circuit 4 as the output of the multiplexer 41.

The other configurations are similar to the circuit shown in FIG. 2.

In this circuit as well, when the strobe signal S is at a high potential, the input data D is selected by the AND-NOR composite gate 42, and when the strobe signal S is at a low potential, the latch output data Q input as feedback is selected by the AND-NOR composite gate 42. Selected by NOR composite gate 42.

Further, the operation of the dynamic holding circuit 4 is similar to that described above.

FIG. 6 is a circuit diagram showing an example in which latch circuits are arranged before and after the D latch circuit shown in FIG. 2, respectively.

The D latch circuit 50 is the D latch circuit shown in FIG. 2, and the latch circuits 51 and 52 arranged before and after the D latch circuit 50 are the same as the latch circuit 5 in FIG.
It has the same configuration as 1.52.

In this circuit, when the clock signal CLK2 falls, the transfer gate 15 is also immediately turned off, but the inverter 55. Transfer gate 11 and inverter 1
2, a delay of three stages of gates occurs. Therefore, after the clock signal CLK2 falls, the clock signal C
Even if the period until LKI rises is O, this circuit will not malfunction.

[Effects of the Invention] As described above, according to the present invention, the selection operation of the multiplexer is performed only by the strobe signal, and the latch operation is performed by directly supplying the clock signal to the dynamic holding circuit arranged at the output stage. By doing so, the delay time from the input of the clock signal until the latch output data changes can be significantly shortened, and the operating speed can be improved.

Further, according to the present invention, the holding operation in the dynamic holding circuit is performed immediately after inputting the clock signal.
Even when applied to a circuit in which other latch circuits are disposed at the preceding and following stages, the operating speed can be improved by shortening the period during which both the two-phase clocks are at low potential.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a D latch circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram showing details of the D latch circuit, and FIG. 3 is a block diagram of a D latch circuit according to a second embodiment of the present invention. 4 is a circuit diagram of a D latch circuit according to a third embodiment of the present invention, and FIG. 5 is a circuit diagram of a D latch circuit according to a fourth embodiment of the present invention.
A circuit diagram of the latch circuit, Fig. 6 is a circuit diagram of an application circuit using the D latch circuit of the first embodiment, Fig. 7 is a circuit diagram of a conventional D latch circuit, and Fig. 8 is a circuit diagram of the D latch circuit of the first embodiment. FIG. 9 is a timing diagram showing the operation of the circuit shown in FIG. 9. FIG. 9 is a circuit diagram of an application circuit using the same D latch circuit. FIG. 10 is a timing diagram showing the operation of the circuit shown in FIG. it i al 1 b+ IC; data input terminal, 2゜2a, 2b; strobe input terminal, 3.21
, 31.41, 61; Multiplexer, 4, 22; Dynamic holding circuit, 5.5a, 7a, 8a, 9a; Clock input terminal, 5b, 7b, 8b, 9b; Clock inversion input terminal, 6; Output terminal, 11゜I4, 15.33a
~33c, 54+ 57.64+67.71.76
) Transfergate, 12゜13.16.34a
~34c, 35.36a, 36b, 43, 53, 55,
56.58, 63, 65.66.72, 73, 75; Inverter, 23-25; Clocked inverter, 37a
~37d. 62.74; NAND gate, 42; AND-NOR composite gate, 50, 70; D latch circuit, 51.52; latch circuit

Claims (3)

[Claims] (1) A multiplexer that selects and outputs one or more input data using a strobe signal and inputs latch output data as a feedback input, and dynamically holds the output of this multiplexer according to a clock signal and outputs it as the latch output data. A D latch circuit comprising a dynamic holding circuit. (2) the dynamic holding circuit includes a transfer gate having a dynamic holding function that selectively transfers the output of the multiplexer according to the clock signal;
2. The D latch circuit according to claim 1, further comprising an inverter that inverts the output of the transfer gate and outputs the inverted output as the latch output data. (3) The dynamic holding circuit includes a clocked inverter having a dynamic holding function that selectively inverts and outputs the output of the multiplexer according to the clock signal, and an output of the clocked inverter that is inverted and output as the latch output data. 2. The D latch circuit according to claim 1, wherein the D latch circuit comprises an inverter.