JPH04362784A - Pattern inspection method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern verification method, and more particularly to a method for verifying a mask pattern of a semiconductor integrated circuit or a pattern of a printed circuit board.

0002

2. Description of the Related Art A mask pattern for a semiconductor integrated circuit is composed of many layers, and when verifying a mask pattern, these layers are usually processed using logical sum (OR), logical product (AND), and NAND (ANDNOT). ), exclusive OR (EXOR), and other logical operations are performed to perform geometric rule checks and electrical connection checks.

FIG. 8 shows a typical mask pattern verification processing procedure. Further, FIGS. 5 and 6 show an example of a geometric rule check based on a mask pattern verification processing procedure.

In the conventional processing procedure, as shown in FIG. 8, a mask pattern is first divided into layers, and logical operations are performed on the layers according to the purpose of processing. Then, checks are performed depending on the processing purpose, that is, geometric rule checks and electrical connection checks. The results are displayed on a CRT or the like.

A geometric rule check for the two mask pattern layers A and B will be explained with reference to FIGS. 5 and 6. The rules are shown in Figures 5(a) to (f).
There is something shown below. Figure 5(a) checks the width of A, (
b) Checks the width of B, (c) checks the spacing of A, (d) checks the spacing of B, (e) checks the width of C for the part C where A and B overlap, (f ) are A and B
Assume that the interval between C and C is checked for the overlapping portion of C.

[0006] As shown in FIG. 6, the geometric rule check process first divides layer A according to a mask pattern as process 1. Then, as process 2, layer B is divided based on the mask pattern.

Next, in process 3, A and B are ANDed to obtain the layer C.

After that, the width of A is determined in process 4, and the width of B is determined in process 5.
The width of C is checked in process 6, the width of A is checked in process 7, the width of B is checked in process 8, and the width of C is checked in process 9.

Next, in process 10, the result of process 4, in process 11, the result of process 5, in process 12, the result of process 6, in process 13, the result of process 7, and in process 14, The results of process 8 and process 9 are displayed in process 15, respectively.

[0010] Conventionally, verification of a mask pattern consists of processes 1 to 1.
The processes up to 15 are performed sequentially.

Of these processes, process 3 cannot be performed unless processes 1 and 2 are completed, and processes 4 to 9 require processes 1, 2, and 3 to be completed. Furthermore, processes 10 to 15 must similarly have completed processes 4 to 9.

However, processes 1 and 2 may be performed separately, and the same applies to processes 4 to 9.

[0013]

[Problem to be solved by the invention] Logical operations of layers,
Geometric rule checks and electrical connection checks may require the use of the processing results from the previous stage, but
Some can be processed completely separately.

Conventionally, in a workstation (WS) having a single arithmetic unit, the above-mentioned processing had to be performed sequentially, and due to the influence of recent high integration of semiconductors, the processing time became enormous. It has become.

[0015] In addition, a WS that incorporates multiple arithmetic units can perform parallel processing and speed up processing, but the equipment is expensive and there are problems with flexible configurations, ie, expandability. was there.

[0016]Furthermore, recently, low-priced and relatively high-performance WS have been sold, and by introducing a large number of such WS, it is easy to allocate a WS to each semiconductor integrated circuit design engineer. It has become to. Such WSs are used for many purposes, but because most of them have personal specifications, their operating rates are not very high, and there is a considerable amount of time when they are not in use.

[0017] Focusing on the above points, the present invention aims to search for a vacant WS and speed up master pattern verification, which takes an enormous amount of processing time.

[0018]

[Means for Solving the Problems] A pattern verification method of the present invention connects a plurality of workstations equipped with arithmetic units that perform arithmetic operations and control for verifying mask pattern data stored in a storage device through a network. , at least one workstation manages the verification processing procedure, and when the verification processing is a processing procedure that can be processed in parallel, another workstation with a smaller load is used to perform the parallel processing.

Furthermore, at the workstation that manages the above-mentioned verification processing procedure, the processing capacity and amount of data to be processed are compared with each workstation that performs parallel processing, so that the processing completion time at each workstation is equalized. It is characterized by distributing processing to.

[0020]

[Operation] According to the present invention, when parallel processing is possible, the processing speed is improved because parallel processing is performed by a plurality of WSs. In addition, by selecting a WS in consideration of the degree of use, etc.
can improve the operating rate.

[0021]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the overall configuration of an apparatus used in the verification method of the present invention. As shown in FIG. 1, a plurality of workstations (WS) 10-1, 10
-2, 10-3, and 10-4 are connected by network 1.

[0023] Each workstation (WS) 10-1...
As shown in FIG. 2, the arithmetic device 11, the input device 12,
It is composed of a storage device 13, a display device 14, and the like.

The calculation device 11 receives data from the storage device 13 that stores mask pattern data and circuit connection information, and performs calculations or control to verify the mask pattern data.

The display device 14 is composed of a CRT, a liquid crystal panel, etc. that visually displays the results of calculations performed by the calculation device 11.

The input device 12 has an input section such as a keyboard and a mask, and inputs instructions and the like for performing verification.

Note that the display device 14 and input device 12 are not required for all WSs, and may be omitted depending on the application.

The present invention has the configuration shown in FIGS. 1 and 2, and operates according to the processing procedure shown in FIG. A user uses a WS that supports verification processing as a server WS, and manages and executes the processing. A WS connected to another network is assumed to be a client WS.

First, the server WS determines a processing procedure depending on the type of verification and the rules. Next, it is determined whether the processing must be performed sequentially or whether it can be processed in parallel. In the case of sequential execution, it is executed by the server WS. When parallel processing is possible, it is checked whether other users are using the client WS, or whether the client WS is using it at a low level.

First, a method for checking the client WS will be explained with reference to FIG. Create a list of WSs that will be client WSs in advance, and check from this list. At this time, not all WSs connected to the network are targeted. Then, check whether there is a user. That is, it is checked whether there is a logged-in user.

[0031] As a result of the check, if there is no user, it can be used as a client WS. Furthermore, if there is a user, the frequency of use of the computing device is checked, and if the frequency is below a certain level, it is assumed that the computing device can be used as a client WS. The determination value of this frequency is determined in advance, and the frequency is not an instantaneous value but an average value over a certain period of time in the past.

According to FIG. 4, if the WS is checked and there is a WS that can be used as a client WS, a plurality of WSs including the server WS and the client WS can be used.

Next, since there may be differences in the processing capacity of available WSs, processing is allocated to each WS according to the processing capacity. To explain processing allocation based on processing capacity, the processing capacity such as processing speed and storage device capacity may differ depending on each WS, and the scale of verification processing such as the number of figures and the number of processes may vary depending on the processing. different. Therefore, the server WS takes these into account and allocates a WS for appropriate processing. That is, the WS is allocated so that the processing end time of each WS is equalized by predicting the processing end time.

[0034] Once the allocation is determined, the client WS
transfers the data necessary for processing to and starts execution. At this time, since the server WS holds the data itself, no transfer is necessary. Therefore, the server WS can execute it immediately. Further, the client WS transfers the results to the server WS after the processing is completed.

These processes are repeated until the preprocessing is completed, and finally, the server WS displays the execution results to the user and ends the process.

Specifically, FIG. 7 shows an example of the processing shown in FIGS. 5 and 6. Processes 1 and 2 can be performed in parallel, so if there is a client WS, the processes are performed in parallel. Next, since processing 3 cannot be processed in parallel, it is executed by the server WS. Processes 4 to 9 can be processed in parallel, so if there is a client WS, the processes are performed in parallel. At this time, it is ideal if there are a maximum of five client WSs, but if there are fewer than five, the processing is performed by dividing. For example, if there are two client WSs, three processes can be performed including the server WS, so processes 4, 5, and 6 are executed separately, and processes 7, 8, and 9.)Finally, processes 10 to 15 are executed separately. The processing is performed by the server WS and the execution is ended. Note that when processing 3 is executed on the server WS, processes 4, 5, 7, and 8 can also be executed simultaneously if there is a client WS, but in the above embodiment, such an example of processing is shown to simplify the explanation. .

The operation of the present invention is as described above, but as another variation, the server WS mainly only manages the processing procedure except when there is no client WS, and the actual processing is performed by the client WS. It is also possible. At this time, since the load on the server WS is lightened, the user can perform other processes other than verification.

[0038]

As described above, the present invention enables processing to be efficiently distributed and executed by a plurality of WSs in mask pattern verification, thereby reducing processing time. Furthermore, the utilization rate of WS resources can be improved without interfering with the processing of people using other WSs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall structure of a device used in the present invention.

FIG. 2 is a block diagram showing the configuration of a workstation.

FIG. 3 is a flowchart showing the processing operation of the present invention.

FIG. 4 is a flowchart showing the operation of checking a client workstation in the present invention.

FIG. 5 is a schematic diagram for explaining the rules of geometrical checking.

FIG. 6 is an explanatory diagram for explaining a geometric check processing procedure.

FIG. 7 is an explanatory diagram for explaining parallel processing of the geometric check in FIG. 6;

FIG. 8 is a flowchart showing a conventional verification method.

[Explanation of symbols]

1 Network 10-1 Workstation 10-2 Workstation 10-3 Workstation 10-4 Workstation

Claims (2)

[Claims] Claim 1: A plurality of workstations each equipped with an arithmetic unit that performs arithmetic operations and control for verifying mask pattern data stored in a storage device are connected via a network, and at least one workstation performs verification processing procedures. A pattern verification method characterized in that, in addition to performing management, if the verification processing is a processing procedure that can be processed in parallel, parallel processing is performed using another workstation with a small load. Claim 2: A workstation that manages the verification processing procedure compares the processing capacity of each workstation that performs parallel processing and the amount of data to be processed, so that the processing completion time at each workstation is equalized. 2. The pattern verification method according to claim 1, further comprising distributing the processing to the pattern verification method.