JPH04362811A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a through-current flowing from a power supply to a ground terminal transiently in a push-pull circuit. CONSTITUTION:When signals at output terminals 10, 10' of an output control signal circuit 4 are set respectively to '0', '1' and signals at output terminals 8, 8' of gate driving circuits 3, 3' are set respectively to '0', '1', an N-channel MOS transistor(TR) 1 is turned on and an N-channel MOS TR 2 is turned off. When the signals at the output terminals 10, 10' are changed respectively from '0' to '1' and from '1' to '0', the potential at the output terminal 8 of the gate driving circuit 3 cannot be changed from '0' to '1' till the gate potential of the output terminal 8' of the gate driving circuit 3' reaches a prescribed voltage or below, and the N-channel MOS TR 1 remains to be turned off as it is. Thus, before the N-channel MOS TR 2 is turned off, since the MOS TR 1 is not turned on, a through-current is prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a push-pull circuit in which two MOS transistors are arranged in series.

0002

2. Description of the Related Art Conventionally, in this type of semiconductor device, as shown in FIG. and the second NchMO
are respectively connected to the gates of S transistor 2,
The first and second NchMOS transistors were driven only by the control signal of the gate drive circuit.

Furthermore, in actual use, as shown in FIG.
An H bridge circuit was constructed using the S transistor 14.

During normal operation, the diagonal gate drive circuits are turned "on" and "off" at the same time to drive the load.

[0005]

However, in the conventional semiconductor device described above, as shown in FIG. 4, the first MOS transistor 1 and the second MOS transistor 2 are turned on simultaneously during phase switching. In order to be able to be in a state where
Transient current (through current:
There was a drawback that Im (several hundred mA to several tens of amperes) would flow.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to provide a novel semiconductor device that makes it possible to eliminate the above-mentioned disadvantages inherent in the conventional technology. There is a particular thing.

[0007]

[Means for Solving the Problems] In order to achieve the above object, the semiconductor device according to the present invention disables the other MOS transistor when one MOS transistor is operating so as to prevent the through current Im. It is configured with a device for putting it into operation.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

Referring to FIG. 1, 1 and 2 are N channels (
MOS transistors 3 and 3' (hereinafter referred to as Nch) are gate drive circuits that drive the gates of Nch MOS transistors 1 and 2, respectively. Output terminals 8, 8' of gate drive circuits 3, 3' are connected to inverters 6', 6
are connected to the inputs of the inverters 6' and 6, respectively.
The outputs of are connected to one input of AND gates 5', 5, respectively, and the output terminals 10', 10 of output control signal circuit 4 are connected to the other inputs of AND gates 5', 5, respectively. The outputs of the AND gates 5, 5' are connected to input terminals 9, 9' of the gate drive circuits 3, 3', respectively.

Output terminals 10, 10 of the output control signal circuit 4
' signals are "0" and "1", respectively, and signals of output terminals 8, 8' of gate drive circuits 3, 3' are "0" and "1", respectively.
When set to "0" and "1", NchMOS transistor 1 is "on" and NchMOS transistor 2 is "off".Next, the signals at output terminals 10 and 10' change from "0 to 1" and "1", respectively. →0", the potential at the output terminal 8 of the gate drive circuit 3 cannot change from "0 to 1" until the gate potential at the output terminal 8' of the gate drive circuit 3' falls below a certain voltage. , the first N
The chMOS transistor 1 remains in the "off" state. Therefore, the second NchMOS transistor 2 is “off”
Since the second MOS transistor 1 is not turned on before the second MOS transistor 1 is turned on, it is possible to prevent a through current.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

Referring to FIG. 2, this second embodiment:
From the first embodiment shown in FIG.
This is a circuit in which the ND gate 5' is removed. First NchM
The source of the OS transistor 1 is connected to the connection terminal, but the source of the second MOS transistor 2 is connected to the ground terminal. Off” Speed is slow. Therefore, the first NchMOS
Before transistor 1 turns on, the second NchMOS
If the transistor 2 can be turned off, the through current can be prevented, so even if the inverter 6' and the AND gate 5' are omitted, the through current can be substantially prevented.

[0014]

[Effects of the Invention] As explained above, according to the present invention,
In a push-pull circuit in which two MOS transistors are arranged in series, the output terminal of the first gate drive circuit of the first MOS transistor is connected to the inverter gate and the
By connecting to the input terminal of the second gate drive circuit through the ND gate, the M on the source side and the sink side
Since the OS transistors do not turn on at the same time, it is possible to prevent a through current from flowing transiently from the power supply to the ground terminal as shown in FIG. 4.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing a first embodiment according to the present invention.

FIG. 2 is a block configuration diagram showing a second embodiment according to the present invention.

FIG. 3 is a power supply current waveform diagram in a conventional circuit block.

FIG. 4 is a power supply current waveform diagram in the circuit block of the present invention.

FIG. 5 is an H-bridge circuit diagram.

FIG. 6 is a conventional circuit block diagram.

[Explanation of symbols]

1...First NchMOS transistor 2...Second NchMOS transistor 3, 3', 23, 23'...Gate drive circuit 4...Output control signal circuit 5, 5'...AND gate 6, 6'...Inverter 7...First Output terminals 8, 8'...Output terminals 9, 9' of the gate drive circuit...Input terminals 10, 10' of the gate drive circuit...Output terminal 11 of the output control signal circuit...Power terminal 12...Ground terminal 13...Third terminal NchMOS transistor 14...fourth N
chMOS transistor 15...second output terminal

Claims (2)

[Claims] 1. A first MOS transistor having a drain connected to a power supply terminal, a source connected to an output terminal, and a gate connected to an output terminal of a first gate drive circuit; a first MOS transistor having a drain connected to the output terminal and a source connected to the output terminal; a second MOS transistor whose gate is connected to a ground terminal and whose gate is connected to an output terminal of a second gate drive circuit, wherein the output terminal of the second gate drive circuit is connected to a first inverter gate and a second MOS transistor whose gate is connected to an output terminal of a second gate drive circuit; A semiconductor device, wherein the semiconductor device is connected to an input terminal of the first gate drive circuit through a first AND gate. 2. The output terminal of the first gate drive circuit is further characterized in that the output terminal of the first gate drive circuit is connected to the input terminal of the second gate drive circuit through a second inverter gate and a second AND gate. 1. The semiconductor device according to 1.