JPH043639A - Demodulating circuit - Google Patents

Abstract

PURPOSE:To apply a demodulating circuit to a wide-ranging signal to be modulated by providing a complex multiplier and an automatic frequency control loop, which negatively feed back the output to the input side so that the frequency error of the complex multiplier is 0, between A/D converters, which digitize a quasi-synchronism detection signal, and channel filters. CONSTITUTION:A first complex multiplier 6-1 is provided between A/D converters 5-1 and 5-2 and channel filters 13-1 and 13-2, and the automatic frequency control loop which negatively feeds back the output of the complex multiplier 6-1 to the input side is added there. Since this AFC loop includes a digital integrator 9-2, the operation to completely eliminate the frequency error is performed. when the frequency error is 0, a control signal generating circuit 16 is operated as an integrator, and as the result, this loop is a phase locked loop and the frequency error is kept at 0. Thus, the same system is applied to very wide-ranging kinds of signal to be modulated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a demodulation circuit that performs digital signal processing on a quasi-synchronous detection signal to reproduce the signal, and particularly relates to a demodulation circuit suitable for mobile communications.

(Prior Art) Digital signal processing technology has been progressing rapidly in recent years, and if this technology is applied to signal reproduction, a highly versatile demodulation circuit can be realized. This type of demodulation circuit is configured, for example, as shown in FIG. 2, to first perform quasi-synchronous detection on a received modulated signal, and then to perform digital signal processing on the quasi-synchronous detected signal.

FIG. 2 shows an example of a general configuration.

In FIG. 2, a local oscillator 1, a π/2 phase shifter 2,
Mixers 3-1 and 3-2 collectively form a quasi-synchronous detection circuit, and convert the received modulated signal into two local signals whose phases differ by π/2 (the frequency is approximately equal to the carrier frequency of the received modulated signal). The frequency is converted to a baseband signal by

Each of the two outputs (quasi-synchronous detection signals) of this quasi-synchronous detection circuit is filtered by a low-pass filter (L P F >4-1 and 4-2 corresponding to each other) and then passed through an A/D converter 5- 1 and same 5-
Enter the corresponding information in 2. A/D converter (5-1,
In step 5-2), the input baseband quasi-synchronous detection signal is sampled at the sample timing from the sample timing generation circuit 15 and converted into a digital signal. This sampling rate is at least twice as fast as the occupied bandwidth of the received modulated signal, and is usually eight times as fast as the occupied bandwidth of the received modulated signal.

Each output of the A/D converter (5-1, 5-2) is matched filtered by a corresponding one of the channel filters (13-1, 13-2) and input to the demodulator 14.

The demodulator 14 reproduces and outputs P channel and Q channel modulated data and clocks by synchronous detection or asynchronous detection (delay detection, frequency discrimination detection, etc.).

In special cases, the reproduced clock may be multiplied by m and used as the sample timing of the A/D converters (5-1, 5-2).

(Problems to be Solved by the Invention) Incidentally, in quasi-synchronous detection, a frequency error between the received modulated signal and the local signal is unavoidable, but this causes the following inconvenience.

In other words, mismatching occurs in the channel filter, causing deterioration in demodulation characteristics. In addition, in demodulators, if the synchronous detection method is used, it becomes difficult to synchronize the carrier recovery circuit, and if the asynchronous detection method is used, offsets occur due to frequency and phase shifts, and in digital signal transmission, the bit error rate increases. cause significant deterioration. In particular, when the frequency difference becomes larger than the signal transmission speed to some extent, it becomes difficult to distinguish between a phase change due to a modulated signal and a phase change due to a frequency error, and the demodulator becomes inoperable.

Conventionally, in order to eliminate the negative effects caused by this frequency error, the local oscillator was placed in a constant temperature oven to make it more stable and actively suppress the occurrence of frequency error, or the transmission signal was preceded by an unmodulated signal. Various measures have been taken to facilitate the initial synchronization of the demodulator circuit.

However, in mobile communications, mobile devices are required to be small and inexpensive, so it is difficult to employ highly stabilized local oscillators, which are expensive and tend to be large. Furthermore, in mobile communications, signal power frequently decreases due to trees, buildings, etc., so a method of pre-transmitting an unmodulated signal is no longer effective.

The present invention has been made in view of these problems, and its purpose is to provide a truly versatile digital signal processing type demodulation circuit that can be applied to mobile communications without any problems.

(Means for Solving the Problems) In order to achieve the above object, the demodulation circuit of the present invention has the following configuration.

That is, the demodulation circuit of the present invention includes a quasi-coherent detection circuit that performs quasi-coherent detection of a received modulated signal to form and output two series of baseband signals (complex baseband signals) whose phases differ by π/2; Low-pass filtering the baseband signal counterpart 2
- two A/D converters for digitizing corresponding outputs of the two low-pass filters; and - two A/D converters for digitizing corresponding outputs of the two input series of signals; Matching filter 2
a demodulator that receives the outputs of the two channel filters and regenerates the signal; and a demodulator that integrates the input digital control value and adjusts the phase by π/2 based on the integration result. a control signal generation circuit that forms and outputs two different series of digital control signals (complex control signals); and outputs of the two A/D converters (
a first complex multiplier that generates two series of signals for the two channel filters by complex multiplying a complex output of the control signal generation circuit and a complex output of the control signal generation circuit; two delay devices that delay by one sample time; a second complex multiplier that performs complex multiplication of the complex output of the first complex multiplier and the outputs (complex outputs) of the two delay devices; a digital integrator that integrates the imaginary part output of the complex output of the complex multiplier No. 2; and a loop filter that low-pass filters the output of the digital integrator and outputs the digital control value. That is.

(Function) Next, the function of the demodulation circuit of the present invention configured as described above will be explained.

The demodulation circuit of the present invention employs two A, which digitizes a quasi-coherent detection signal in a demodulation circuit that employs a quasi-coherent detection method.
Focusing on the fact that the output of the /D converter is a complex signal, we
A first complex multiplier is provided between the two A/D converters and the two channel filters, and the output of the first complex multiplier is negatively fed back to the input side, so that the output of the first complex multiplier is Automatic frequency control that operates to reduce frequency errors to zero (
AFC) loop is added.

That is, the frequency error discrimination voltage obtained as the imaginary part output of the second complex multiplier is smoothed by a digital integrator and a loop filter. This is integrated in the control signal generation circuit,
Two series of digital control signals are formed which are complex multiplied by the outputs of the two A/D converters. Since this AFC loose includes a digital integrator, an operation is performed to completely eliminate the frequency error. And when the frequency error becomes zero,
As a result of the control signal generation circuit operating as an integrator, the loop becomes a phase-locked loop and maintains the frequency error at zero.

Thus, according to the present invention, it is possible to solve the problem of mismatching of channel filters and the problem of difficulty in locking in synchronization of a demodulator, which have been difficult to solve in the past.

Further, since the frequency control operation is performed on the modulated signal, normal signal acquisition can be maintained even when the power of the received signal frequently decreases as in mobile communication.

Furthermore, since the frequency control operation described above is universally possible regardless of whether the modulation method is analog or digital, the same method can be applied to an extremely wide variety of modulated signals.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a demodulation circuit according to an embodiment of the present invention. In this embodiment circuit, the received modulated signal is digitally modulated as in the conventional example, but in the demodulation circuit shown in FIG. , a (first) complex multiplier 6-1 is provided between the A/D converter (5-1, 5-2) and the channel filter (+3-1.13-2), and this complex multiplier 6 -1
Automatic frequency control (AFC) that negatively feeds back the output of
>This is a loop added. Hereinafter, A according to the present invention
FC operation will be explained.

Since the received modulated signal is a two-series signal (complex signal) with a phase difference of π/2, the A/D converter (5-1゜5-2)
The output W, (t) of is generally W + (t) = (x (
t)+jy (t))exp Ij (ω1t+θ1)
) can be expressed as Here, X (t) and y (t) are the original signals of the modulated signal (i.e., modulated signals), each taking a real value, and their autocorrelation function is defined as , and their correlation length is T. Then, holds true. Also, x (t), y
(t) are mutually independent and . In addition, in equation (2) and equation (B), □ indicates a time average.

The control signal generation circuit 16 includes an integrator 9-1, a sine signal generation circuit 7, and a cosine signal generation circuit 8. The integrator 9-1 includes an adder 11-1 whose one input is the output (digital control value) of the loop filter 12, and an adder 11-1 which delays the output of the adder 11-1 by one sample time.
It is constituted by a loop circuit with a delay device 10-1 which is applied to the other input of 1-1. The sine signal generation circuit 7 and the cosine signal generation circuit 8 are, for example, ROM (Read Only M
It receives the output of the integrator 9-1 as an address signal and outputs two series of digital control signals having phases different by π/2. The frequency of the local signal is ω,
If the phase is θL, the output WL of the control signal generation circuit 16
(t) is WL(t) = e Xp (j (ωtt +
It can be expressed as θL)+ (5).

Therefore, the output W0(t) of the complex multiplier 6-1 is Wo(t
) =Wl(t)・WL(t)'=(x(
t)+jy (t))exp (j (ωet+θe)
). Here, ≠ represents a complex conjugate and is also.

Delay devices 10-3 and 10-4, like delay device 10-1, delay the input signal by one sample time and output it, but the clock period is T, and sampling is performed at m times this time. Assuming that each output of the complex multiplier 6-1 is delayed by T/m.

Therefore, the output Wd(t) of the complex multiplier 6-2 is = (R
xx(T/m)+Ryy(T/m))exp(j
ω, T/m), and its imaginary part output (6) becomes Va = I - (Wd(t) 1 ). That is, a frequency error discrimination voltage can be obtained.

The integrator 9-2, like the integrator 9-1, has an adder 11-
2 and a delay device 1O-2, and its output is given to a loop filter 12. That is, equation (9)
The frequency error discrimination voltage represented by
Enter. And control signal generation times F! At @16,
Frequency error ω in equation (9). A control signal is generated to make the value zero. In particular, since the AFC loop described above includes the integrator 9-2, the frequency error ω.

It operates so that it becomes completely zero.

Next, when the frequency error ω6 becomes zero, equation (9) becomes VP(
t) = (Rx, (T/+++)+Ryy(T/m))
sin (θ, (1)-θe(t-T/m))"
= (RXX(T/m)+Ryy(T/m)l(
θ, (t)-θe(t-T/m)). That is,
The variable Z of Z transformation is Z=exp(jωT/m) (I
I), the transmission interval number Vd(Z) is Vd(Z)=Kd(1-Z-')e,(Z). However, K6 is the detection sensitivity, Kd = RXX (T/m) + Ryy (T/m)
(13).

However, the transfer function of the integrator 9-2 is, and the output of the integrator 9-2 is T+(Z)・Va(Z) =Kd・θ,(Z)
(+5), and a mere phase error is produced.

As a result, the control signal generation circuit 16 starts operating as an integrator. That is, after the frequency error becomes zero, the AFC loop described above operates as a phase-locked loop and continues to maintain the frequency error at zero.

The synchronization range of the AFC operation described above can be determined as follows. From equation (9), (J)eT/ml≦π
(16) Therefore, 1ω and 1≦early (17). For example, if T is the clock period and m=4, the synchronization range is 1f, 1≦-2-(18), and it can be seen that synchronization is possible even for frequency errors greater than the tarok frequency.

In addition, in order for the circuit of the present invention to operate, the autocorrelation function only needs to be a real value, and specifically, the equation () needs to hold true, and it is sufficient to determine whether the modulation method is digital or analog. No question. Therefore, the demodulation circuit of the present invention is applicable to an extremely wide range of modulated signals.

(Effects of the Invention) As explained above, according to the demodulation circuit of the present invention, in a demodulation circuit that employs a quasi-coherent detection method, a complex signal is generated between an A/D converter for digitizing a quasi-coherent detection signal and a channel filter. By providing a multiplier and an automatic frequency control loop that negatively feeds the output back to the input side in order to zero out the frequency error in the output of this complex multiplier, the problem of mismatching of channel filters, which was previously difficult to solve, is solved. This can solve the problem of difficulty in synchronizing the demodulator.

Further, since the frequency control operation is performed on the modulated signal, normal signal acquisition can be maintained even when the power of the received signal frequently decreases as in mobile communication.

Furthermore, since frequency control operation is universally possible regardless of whether the modulation method is analog or digital, the same method can be applied to an extremely wide variety of modulated signals, etc. There is.

[Brief explanation of the drawing]

FIG. 1 is a configuration block diagram of a demodulation circuit according to an embodiment of the present invention, and FIG. 2 is a general configuration block diagram of a conventional demodulation circuit. 1...Local oscillator, 2...π/
2 phase shifter, 3-1.3-2...mixer, 4-
1.4-2...Low pass filter (LPF), 5-
1.5-2...A/D converter, 6-1.6-2.
...Complex multiplier, 7...Sin signal generation circuit, 8...Cos signal generation circuit, 9-
1.9-2...Integrator, 10-1 to 10-4
...Delay device, ll-1,112...
Adder, ]2...Loop filter, 131
゜l3-2...Channel filter, 14...
... Demodulator, 15. Sample timing generation circuit, 16. Old control signal generation circuit. Agent Patent Attorney Yoshihiro Hachiman

Claims (1)

[Claims] a quasi-coherent detection circuit that performs quasi-coherent detection on a received modulated signal to form and output two series of baseband signals (complex baseband signals) whose phases differ by π/2; two low-pass filters for performing bandpass filtering; and two for digitizing corresponding outputs of the two low-pass filters;
two A/D converters; two channel filters that match-filter the corresponding two series of input signals; and a demodulator that receives the outputs of the two channel filters and regenerates the signals. In a demodulation circuit equipped with;; the input digital control value is integrated, and the phase is determined based on the integration result by π/
2 different 2 series digital control signals (complex control signals)
a control signal generation circuit that forms and outputs; the two A/Ds;
a first complex multiplier that performs complex multiplication of the output (complex output) of the converter and the complex output of the control signal generation circuit to generate two series of signals for the two channel filters; the first complex multiplier; two delay devices that delay the complex output of the multiplier by one sample time; a second complex multiplier that performs complex multiplication of the complex output of the first complex multiplier and the outputs (complex outputs) of the two delay devices; a digital integrator that integrates the imaginary part output of the complex output of the second complex multiplier; a loop filter that low-pass filters the output of the digital integrator and outputs the digital control value; A demodulation circuit characterized by comprising: