JPH04364052A - Mounting method for semiconductor element - Google Patents
Mounting method for semiconductor elementInfo
- Publication number
- JPH04364052A JPH04364052A JP3138084A JP13808491A JPH04364052A JP H04364052 A JPH04364052 A JP H04364052A JP 3138084 A JP3138084 A JP 3138084A JP 13808491 A JP13808491 A JP 13808491A JP H04364052 A JPH04364052 A JP H04364052A
- Authority
- JP
- Japan
- Prior art keywords
- tab
- semiconductor
- semiconductor element
- mounting
- semiconductor elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は半導体素子の実装方法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting semiconductor devices.
【０００２】0002
【従来の技術】従来、半導体素子の実装方法としては、
図２示すように回路基板１上に、半導体素子３を接着搭
載し、回路導体２を介しボンディングワイヤー８を用い
て素子間の相互接続を実現したり、図３に示すように回
路導体２を介さずに相互接続用ボンデイングワイヤー９
を用いて、素子間を直接接続していた。[Prior Art] Conventionally, as a method for mounting semiconductor elements,
As shown in FIG. 2, a semiconductor element 3 is adhesively mounted on a circuit board 1, and interconnection between the elements is realized using a bonding wire 8 via a circuit conductor 2, or as shown in FIG. Bonding wire 9 for interconnection without intervening
was used to directly connect the elements.
【０００３】0003
【発明が解決しようとする課題】上述した従来の半導体
素子の実装方法では、相互に依存する機能を持つ半導体
素子を使用する際には、回路基板上に実装した後で機能
試験を行わなければならなかった。また、実装面積も半
導体素子の大きさの倍必要であるという問題点があった
。[Problems to be Solved by the Invention] In the conventional semiconductor device mounting method described above, when semiconductor devices with mutually dependent functions are used, a functional test must be performed after mounting them on a circuit board. did not become. Further, there is a problem in that the mounting area needs to be twice the size of the semiconductor element.
【０００４】本発明の目的は、半導体素子単体での機能
試験の実施及び半導体素子の実装面積を削減することが
可能な半導体素子の実装方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for mounting a semiconductor element, which allows a functional test to be performed on a single semiconductor element and a reduction in the mounting area of the semiconductor element.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体素子の実
装方法は、機能的に相互に依存し相対する１対の半導体
素子のそれぞれの接続パッド上に半田バンプを形成し、
ＴＡＢリードフレームに接続されたインナーリードを前
記半田バンプによって挟むようにして前記半導体素子の
相互間を接続する構成であり、また前記半導体素子の相
互間を接続し機能試験完了後、前記ＴＡＢリードフレー
ムにアウターリードを接続し、このアウターリードを前
記半導体素子を実装するための回路基板の外部端子へ接
続する構成である。[Means for Solving the Problems] A semiconductor device mounting method of the present invention includes forming solder bumps on respective connection pads of a pair of functionally mutually interdependent and opposing semiconductor devices;
The semiconductor elements are connected to each other by sandwiching the inner leads connected to the TAB lead frame between the solder bumps, and after the semiconductor elements are connected to each other and a functional test is completed, an outer lead is attached to the TAB lead frame. The outer lead is connected to an external terminal of a circuit board on which the semiconductor element is mounted.
【０００６】[0006]
【実施例】次に本発明について図面を参照して説明する
。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.
【０００７】図１は本発明の一実施例を示す側面図であ
る。図１において、本発明の実装方法は、ＴＡＢアウタ
ーリード６の接続用の回路導体２を形成した回路基板１
上に、機能的に相互に依存し相対する１対の半導体素子
３のそれぞれの接続パッド上に半田ハンプ４を形成し、
ＴＡＢリードフレーム７に接続されたＴＡＢインナーリ
ード５を半田バンプ４によって挟んで接続し、接着搭載
したものである。なお、ＴＡＢリードフレーム７は通常
、半導体素子３の四方に設けられるが、図１では、側面
からみた２個のみを示しており、正面及び背面の２個は
図示を省略してある。FIG. 1 is a side view showing one embodiment of the present invention. In FIG. 1, the mounting method of the present invention includes a circuit board 1 on which a circuit conductor 2 for connecting a TAB outer lead 6 is formed.
forming a solder hump 4 on each connection pad of a pair of functionally interdependent and opposing semiconductor elements 3;
A TAB inner lead 5 connected to a TAB lead frame 7 is sandwiched and connected between solder bumps 4 and adhesively mounted. Note that the TAB lead frames 7 are normally provided on all sides of the semiconductor element 3, but in FIG. 1, only two are shown as seen from the side, and the two on the front and back are omitted.
【０００８】このように、半導体素子３相互間をＴＡＢ
インナーリード５で直接接続する事により、回路基板１
への実装前にＴＡＢインナーリード５による半導体素子
３の機能試験も可能になり、また、回路基板１への実装
後には、その実装面積が半導体素子３の１個分の面積し
か必要でなくなり、半導体素子３を別々に実装した際の
半分の面積で済むことになる。[0008] In this way, TAB is used between the semiconductor elements 3.
By directly connecting the inner lead 5, the circuit board 1
It is now possible to test the functionality of the semiconductor element 3 using the TAB inner lead 5 before mounting it on the circuit board 1, and after mounting it on the circuit board 1, the mounting area only needs to be the area of one semiconductor element 3. The area required is half that of mounting the semiconductor elements 3 separately.
【０００９】なお、本発明は上述した一実施例に限定さ
れるものではなく、発明の要旨を変更しない範囲で種々
変形が可能なことは、言うまでもない。It goes without saying that the present invention is not limited to the one embodiment described above, and that various modifications can be made without changing the gist of the invention.
【００１０】0010
【発明の効果】以上説明したように本発明は、機能的に
相互に依存し相対する１対の半導体素子のそれぞれの接
続パット上に半田バンプを形成し、ＴＡＢリードフレー
ムに接続されたインナーリードを半田バンプによって挟
むようにして半導体素子相互間を接続することにより、
半導体素子の実装面積が従来の半分になる。また、半導
体素子を回路基板に接続する前に、機能試験が行えるよ
うに構成したので、機能不良の半導体素子を回路基板に
実装することが防げるため、製品不良率を低下させるこ
とができるという効果を有する。As explained above, the present invention forms solder bumps on the respective connection pads of a pair of functionally mutually interdependent and opposing semiconductor elements, and connects inner leads connected to a TAB lead frame. By connecting semiconductor elements by sandwiching them between solder bumps,
The mounting area of semiconductor elements is halved compared to the conventional one. In addition, since the structure is configured so that a functional test can be performed before connecting the semiconductor element to the circuit board, it is possible to prevent malfunctioning semiconductor elements from being mounted on the circuit board, which has the effect of reducing the product defect rate. has.
【図１】本発明の一実施例を示す側面図である。FIG. 1 is a side view showing one embodiment of the present invention.
【図２】従来の半導体素子の実装例を示す側面図である
。FIG. 2 is a side view showing an example of mounting a conventional semiconductor element.
【図３】従来の半導体素子の他の実装例を示す側面図で
ある。FIG. 3 is a side view showing another example of mounting a conventional semiconductor element.
１ 回路基板 ２ 回路導体 ３ 半導体素子 ４ 半田バンプ ５ ＴＡＢインナーリード ６ ＴＡＢアウターリード ７ ＴＡＢリードフレーム 1 Circuit board 2 Circuit conductor 3 Semiconductor device 4 Solder bump 5 TAB inner lead 6 TAB outer lead 7 TAB lead frame
Claims (2)
半導体素子のそれぞれの接続パッド上に半田バンプを形
成し、ＴＡＢリードフレームに接続されたインナーリー
ドを前記半田バンプによって挟むようにして前記半導体
素子の相互間を接続することを特徴とする半導体素子の
実装方法。1. Solder bumps are formed on the respective connection pads of a pair of functionally interdependent and opposing semiconductor elements, and inner leads connected to a TAB lead frame are sandwiched between the solder bumps, so that the semiconductor A method for mounting semiconductor devices, characterized by connecting the devices to each other.
完了後、前記ＴＡＢリードフレームにアウターリードを
接続し、このアウターリードを前記半導体素子を実装す
るための回路基板の外部端子へ接続することを特徴とす
る請求項１記載の半導体素子の実装方法。2. After the semiconductor elements are connected to each other and a functional test is completed, an outer lead is connected to the TAB lead frame, and this outer lead is connected to an external terminal of a circuit board on which the semiconductor element is mounted. 2. The method for mounting a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3138084A JPH04364052A (en) | 1991-06-11 | 1991-06-11 | Mounting method for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3138084A JPH04364052A (en) | 1991-06-11 | 1991-06-11 | Mounting method for semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04364052A true JPH04364052A (en) | 1992-12-16 |
Family
ID=15213582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3138084A Pending JPH04364052A (en) | 1991-06-11 | 1991-06-11 | Mounting method for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04364052A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
-
1991
- 1991-06-11 JP JP3138084A patent/JPH04364052A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7112468B2 (en) | 1998-09-25 | 2006-09-26 | Stmicroelectronics, Inc. | Stacked multi-component integrated circuit microprocessor |
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