JPH04364073A - Preparation of mos transistor - Google Patents

Abstract

PURPOSE:To obtain a GOLD structure being excellent in the controllability of film thickness and having a lower gate electrode resistance by the deposition of an even polysilicon film which constitutes an overlap electrode, and by the selective deposition of a metal film having a high melting point on the gate electrode. CONSTITUTION:A gate oxide film 2 is deposited on a p-type substrate 1, and the entire oxide film is then covered with a polysilicon film 3. Phosphorous is then diffused into the polysilicon film 3. Metal having a high melting point, e.g. tungsten 5, is selectively deposited merely on the polysilicon film 3 by the CVD technique. An oxide film 4 is removed, and phosphorous is injected into the p-type substrate 1 with the tungsten 5 as a mask, thereby forming an n<->-drain layer 6. An oxide film 7 is then deposited on the entire surface of this assembly by the CVD technique, and the oxide film 7 and the polysilicon film 3 are etched away, thereby constituting a side wall oxide film 8 and an overlap gate 9.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention is applicable to GOLD (Gate
The present invention relates to a method of manufacturing a MOS transistor having a (Drain Overlap LDD) structure.

0002

[Prior Art] MOS transistor, more specifically, MOS
type field effect transistor (MOSFET; Metal-
Oxide-Semiconductor Field
In an integrated circuit having a MOS transistor as a component, it is common to reduce the element size of a MOS transistor formed on a semiconductor substrate in order to improve the degree of integration of the integrated circuit.

By the way, the basic structure of a MOS transistor is as shown in FIG. 2 as a schematic diagram of a basic n-channel MOS transistor. Oxide film 103
) A so-called MOS capacitor in which a metal electrode (polysilicon electrode 104) is provided is provided with a source 105 that serves as a carrier supply source and a drain 10 that extracts carriers on both sides of the MOS capacitor.
6 is formed of a diffusion layer (N+ diffusion layer 102), and isolation from adjacent MOS transistors is performed by a thick field oxide film 107.

In order to reduce the element dimensions of this MOS transistor, it is essential to reduce the gate length L shown in the figure in addition to reducing the area of the source 105, drain 106, etc.

[0005] The reduction of such a MOS transistor is
As the size is reduced according to the well-known scaling law, especially when the gate length L becomes approximately 1.5 μm or less, current is injected into the gate oxide film 103 due to a phenomenon called hot carriers, which changes the characteristics of the MOS transistor. There are issues that lead to fluctuations.

Although a detailed explanation will be omitted, the electric field in the channel of the MOS transistor is concentrated in the depletion layer region near the drain, for example, in a pentode operation state.

Moreover, this electric field increases in proportion to the reduction of the gate length L, and if the gate oxide film (gate oxide film 103 in FIG. 2) is made thinner as the gate length L decreases, this electric field increases. The increase will further accelerate.

The strong electric field as described above is strong enough to generate sufficient hot carriers, and carriers flowing in the drain depletion layer are accelerated by the strong electric field in the depletion layer.

[0009] Hot carriers with sufficient energy fly out of the channel without being confined within the channel, generate a substrate current, or are injected into the oxide film.

[0010] Some of the carriers injected into the oxide film are trapped or generate surface levels, resulting in a shift in the threshold voltage, a decrease in mutual conductance, and a decrease in the subthreshold region. This causes characteristic deterioration such as increased leakage.

[0011] In order to prevent characteristic fluctuations due to hot carriers in MOS transistors, so-called LDD (
A lightly doped drain (lightly doped drain) structure has been proposed, the idea of which is to alleviate the peak electric field strength in the drain depletion layer that occurs in the pinch-off state.

FIG. 3 shows a typical cross-sectional structure of this LDD structure.
Shown below. In FIG. 3, 201 is a P-type substrate, 202 is an LO
COS oxide film, 207 is gate polysilicon electrode, 20
8 is an N- offset layer, 210 is a gate sidewall oxide film, 211 is a protection oxide film during source/drain ion implantation, 212 is a source/drain layer, 213 is an interlayer insulating film, 214 and 215 are sources・Drain contact holes, 216 and 217 are source ・
This is the drain electrode.

Although this LDD structure prevents the characteristic deterioration caused by hot carriers as described above, when the gate length is further reduced to 0.8 μm or less, the electric field strength in the N-offset layer 208 increases further. , it becomes difficult to maintain the same hot carrier tolerance characteristics as in the past without lowering the power supply voltage.

[0014] Therefore, a GOLD structure in which a gate is overlapped on an N- offset layer (N- drain layer) has been proposed as a way to avoid the above problem (for example, IDM, '87 ,3.1,
P38-41).

A specific example of the method for manufacturing this GOLD structure is shown in FIGS. 4(a) to 4(d). First, as shown in FIG. 4A, after growing a gate oxide film 302 of 150 Å on a P-type (100) substrate 301, a first polysilicon film 302 is grown.
3 is grown to a thickness of 500 Å by LPCVD (low pressure chemical vapor deposition).

[0016] The natural oxide film 304 is removed by air curing.
After growing 10 Å, the second polysilicon 305 and CV
DSiO 2306 is grown, and CVDSiO 2306 is selectively left in the position that will become the gate electrode using well-known photolithographic etching techniques.

Next, as shown in FIG. 4(b), CVDSiO2306 was etched by dry etching with a high selectivity.
Using this as a mask, the second polysilicon 305 is etched.

At this time, the natural oxide film 304 acts as an etching stopper, and the first polysilicon 303 is left without being etched. Thereafter, phosphorus was ion-implanted at an energy of 80 KeV to form the N- drain layer 3.
Get 07.

Next, as shown in FIG. 4(c), CVDS
Grow iO2 on the entire surface, perform RIE etching,
Obtain SiO2308 for the sidewall.

Next, as shown in FIG. 4(d), SEL
OCOS (Selective Oxide Coat)
ingof Silicon gate), 80
Polysilicon is selectively oxidized under wet oxidation conditions at 0° C. as shown at 309 in the figure.

Furthermore, by controlling this oxidation, the overlap length of the gate (first polysilicon) to the drain layer is controlled.

[0022] GOL formed by the method explained above
The D structure has higher reliability and higher g than the above LDD structure.
Both can be achieved.

First, the drain electric field is described in detail in the above-mentioned document IEDM'87, but the overlap gate has an LDD structure (0.0
5 μm), as shown in Figure 6 (for example, 0 μm).
．． 2 μm), the drain electric field is relaxed, resulting in improved drain breakdown voltage and hot carrier resistance.

In addition, the injection of hot carriers into the side surfaces of the gate can be suppressed by the upper gate electrode of the N- layer, and together with the electric field relaxation effect, a high breakdown voltage can be realized.

Next, regarding the resistance of the N- layer, an electric field is applied perpendicularly from the overlap gate to the N- drain part, the surface becomes N+, the resistance decreases, and the gm and channel current increase compared to the LDD. do.

[0026]

[Problems to be Solved by the Invention] However, in manufacturing such a GOLD structure, there are problems described below.

(1) In etching the second layer polysilicon 305, it is difficult to control the stopper oxide film 304 of 5 to 10 Å so that the first layer polysilicon 303 is not etched.

That is, in the GOLD structure, it is necessary that the polysilicon of the gate overlaps the N- drain layer (or N+ drain layer).

In order to obtain this structure, the manufacturing method of the above-mentioned document uses an oxide film 3 of 5 to 10 Å grown on the first polysilicon 303 as shown in FIGS. 4(a) to 4(b).
04 as an etching stopper oxide film, the second polysilicon 305 is etched.

Although the thickness of the second polysilicon is not disclosed in the above-mentioned document, the thickness of the second polysilicon is usually from 3000 Å to 4000 Å, so the thickness of the second polysilicon is the same as that of the first polysilicon. Polysilicon film thickness 50
It is estimated to be 2500 Å to 3500 Å by subtracting 0 Å.

On the other hand, the SiO2 of the stopper is said to be 5 to 10 Å, so during the second polysilicon etching, the selectivity ratio of polysilicon/oxide film is 2500 Å/
A value of 10 Å to 3500 Å/5 Å, or 250 to 700 times as much, is required.

It is difficult to obtain a dry etching apparatus having such a selectivity ratio, and as a result, the remaining film thickness of the first polysilicon varies within a wafer (within a batch). A problem arises in that it cannot be obtained uniformly within the wafer.

In general, wet etching is isotropic etching, so if wet etching with a high selectivity is used, in order to etch polysilicon with a thickness of 2500 Å, the side etching amount will also be 2500 Å, and this side etching amount will be 2500 Å. The etching is CVDSiO as shown in Fig. 4(b).
The same amount is etched from both sides of 2306, totaling 5
000 Å, making it impossible to leave a desired second polysilicon width.

This will be explained using FIG. 7. Assuming that the side etching amount m1 is 2500 Å, and the original dimension m3 of CVDSiO2306 is resolved with the photolithography minimum resolution dimension of 0.5 μm, the remaining second polysilicon width m2 is 0.5-(0 .25×2)
= 0 μm, and the thickness of the second polysilicon is, for example, 0.5 μm.
If you try to leave it, add 1 CVDSiO2306 in advance.
．． The width must be as wide as 0 μm, which impedes improvement in the degree of integration of the device.

(2) If the above-mentioned stopper oxide film 304 is made thicker in order to facilitate the above (1), the first layer polysilicon 303 and the second layer polysilicon 305 will be insulated or Even if it does not, the resistance value will increase.

That is, it is generally difficult to grow a thin oxide film uniformly. According to the disclosed document, this SiO
2304 is said to be obtained by air curing, but normally when a 5-10 Å SiO2 film is obtained by heat treatment,
Even if there is variation within the wafer or SiO2 grows, the film will be sparse.

If it were thicker at the wafer position, a resistance component would enter between the second polysilicon 305 and the first polysilicon 303, as shown by 313 in FIG. 8, and would interfere with the normal operation of the MOS. , in the extreme, it becomes insulated.

Furthermore, if a sparse film is grown, it will not function as an etching stopper during etching, and as a result, a uniform first polysilicon film 303 cannot be obtained.

(3) When using this MOS in a memory device such as DRAM or SRAM, the gate electrode is
Since it is used as a wiring such as a memory word line as well as a gate electrode of an S transistor, it is desirable that its resistance be low.

For this reason, even if the second layer of polysilicon 305 serving as the gate electrode is changed to tungsten silicide (WSiz) or tungsten (W), which has a low resistivity,
When etching tungsten silicide or titanium silicide, the 5
The selectivity with respect to the oxide film 304 of ~10 Å cannot be maintained, and the first polysilicon 303 is etched.

As a result, the remaining film thickness of the first polysilicon 303 varies within a wafer (within a batch), and a problem arises in that a predetermined gate overlap dimension and film thickness cannot be uniformly obtained within a wafer. .

[0042] This invention solves the problems of the prior art, including the difficulty in using a 5 to 10 Å SiO2 film as an etching stopper film, and the problems that occur when the stopper film becomes thick or uneven. The present invention provides a method for manufacturing a MOS transistor that solves the problems of high gate resistance, difficulty in leaving the first polysilicon uniformly, and high wiring resistance when the gate electrode is used as a wiring. .

[0043]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a method for manufacturing a MOS transistor, in which a gate oxide film, a polysilicon film, and a first oxide film are sequentially formed on a semiconductor substrate, and then a gate oxide film, a polysilicon film, and a first oxide film are formed on a semiconductor substrate. A process of removing this first oxide film in the electrode formation region, selectively forming a high melting point metal only in the gate electrode formation region on the polysilicon film, and removing only the first oxide film to form a high melting point metal. After forming an N- drain layer by implanting impurity ions into the semiconductor substrate using a mask, a step of forming a second oxide film and RIE are performed.
This method introduces a step of etching the second oxide film and the polysilicon film by a (reactive ion etching) method to form a sidewall oxide film and an overlap gate.

[0044]

[Operation] According to the present invention, since the above steps are introduced in the method for manufacturing a MOS transistor, the gate electrode forming region of the first polysilicon film formed on the semiconductor substrate is removed, and the first polysilicon film is removed. When a high melting point metal is formed only in the gate electrode formation region on the polysilicon film and the first oxide film is removed, impurity ions are implanted into the semiconductor substrate using the high melting point metal as a mask, thereby forming an N- drain layer. By forming a second oxide film on the entire surface, and removing this second oxide film and polysilicon film to form a sidewall oxide film and an overlap gate, film thickness controllability is improved and the gate electrode Therefore, the above-mentioned problem can be eliminated.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the method of manufacturing a MOS transistor according to the present invention will be described below with reference to the drawings. Figure 1 (a
) to FIG. 1(e) are process cross-sectional views of one embodiment.

First, as shown in FIG. 1(a), a P-type (100) substrate (1 to 2 Ωμm) 1 as a semiconductor substrate has an 8
A gate oxide film 2 of 200 Å is formed under wet conditions at 50° C. for 30 minutes. Next, a polysilicon film 3 of 500 Å is formed on the entire surface by the LPCVD method, and then phosphorus is added to the polysilicon film 3 at 900°C to a phosphorus concentration of 6 x 1020 cm-3.
Diffuse to obtain 1 x 1021 cm-3.

Next, as shown in FIG. 1(b), an oxide film 4 of 3000 Å is formed by the CVD method. Next, the oxide film 4, which will become the gate electrode formation portion, is etched using a known photolithographic etching technique.

Next, by the CVD method, the growth temperature was 320°C.
, pressure 0.1 Torr, gas ratio SiH4 /WF6 =
For example, tungsten (W) 5 is selectively applied to only the polysilicon film 3 as a high melting point metal under the conditions of 1.5.
000 Å is formed.

Thereafter, as shown in FIG. 1C, the oxide film 4 is removed, and phosphorus is implanted at 2×1 at 100 KeV using a known ion implantation technique using tungsten (W) 5 as a mask.
The N- drain layer 6 is formed by implanting into the P type substrate 1 under the condition of 0.013 cm-2.

Next, as shown in FIG. 1(d), C is applied to the entire surface.
After forming an oxide film 7 with a thickness of 4000 Å by the VD method, the oxide film 7 and the polysilicon film 3 are etched using the RIE method to form the sidewall oxide film 8 and the overlap gate. form 9.

[0051] In the subsequent steps, a Gold structure is formed through the SELOCOS process N+ source/drain implantation process, similar to the method shown in the above-mentioned document. The reason for using tungsten (W) for the gate electrode is that when tungsten silicide (WSiz) is selectively formed by the CVD method, the specific resistance is 7 x 10-5Ω.
This is because the resistance value is as high as 5×10 −4 Ωcm. Note that the specific resistance of tungsten (W) under the conditions of the present invention is 8×
It is 10-6 to 1.3 x 10-5 Ωcm.

As described above, in the above embodiment, when leaving the thin polysilicon film 3 that will become the overlap gate electrode 9, etching is performed with a variation of 5% to 10% within the wafer, rather than etching with a variation of 5% to 10% within the wafer. % or less (3%
Since the polysilicon film 3 is formed by the LPCVD method (with a thickness of 5%), the thin polysilicon film 3 that will become the overlap gate electrode 9 can be uniformly formed within the wafer.

Furthermore, in forming the gate electrode, the gate electrode is formed without forming an oxide film for an etching stopper, so that the resistance component of the gate portion can be formed smaller and with less variation than in the past.

Since the material of the gate electrode is a laminated layer of a polysilicon film and a tungsten (W) film, the resistance of the gate electrode can be lowered. For example, in the case of polysilicon, the resistivity of conventional gate electrode materials is 1 x 10-3 to 5
×10-3Ωcm, tungsten silicide (W
Even in the case of Siz), it is ~7 x 10-5 Ωcm, and in this invention, it is 8 x 10-6 to 1.3 x 10-5 Ωcm, which is lower than the conventional value.

[0055]

[Effects of the Invention] As explained in detail above, according to the present invention, a polysilicon film serving as an overlapping gate electrode is uniformly formed, and a high melting point metal film is selectively formed on the gate electrode. Therefore, a GOLD structure with good film thickness controllability and low gate electrode resistance can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view of an embodiment of a method for manufacturing a MOS transistor according to the present invention.

FIG. 2 is a schematic diagram showing the basic configuration of a conventional MOS transistor.

FIG. 3 is a cross-sectional view of a conventional LDD structure.

FIG. 4 is a process cross-sectional view of a conventional method for manufacturing a GOLD structure MOS transistor.

FIG. 5 is an explanatory diagram of the drain electric field of the GOLD structure obtained by the manufacturing method of FIG. 4;

FIG. 6 is an explanatory diagram of the drain electric field of a conventional LDD structure.

FIG. 7 is a cross-sectional view for explaining that the second polysilicon film of the conventional GOLD structure cannot obtain the desired width dimension.

FIG. 8 is a cross-sectional view for explaining that the resistance value of the gate electrode of the conventional GOLD structure is large.

[Explanation of symbols]

1 P-type board 2 Gate oxide film 3 Polysilicon film 4 Oxide film 5 Tungsten 6 N- drain layer 7 Oxide film 8 Sidewall oxide film 9 Overlap gate

Claims (1)

[Claims] 1. A step of sequentially forming a gate oxide film, a polysilicon film, and a first oxide film on the surface of a semiconductor substrate, and removing the first oxide film in a portion that will become a gate electrode formation region, and the steps of: selectively forming a high melting point metal only on the polysilicon film; removing only the first oxide film and implanting impurity ions into the semiconductor substrate using the high melting point metal film as a mask; A method for manufacturing a MOS transistor comprising the steps of forming a second oxide film over the entire surface and then forming a sidewall oxide film on the side surface of the high melting point metal of the overlap gate made of the polysilicon film by RIE.