JPH0441502B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is particularly effective when applied to semiconductor technology and to semiconductor integrated circuits, for example, a technology that is effective when applied to the formation of bipolar transistors in MOS integrated circuits. It is related to.

[Background technology]

In recent CMOS integrated circuit technology, a P-well region is generally formed on an N-type semiconductor substrate.
An N-channel MOSFET is installed in this P-well area.
(insulated gate field effect transistor) is being formed. Therefore, by using this P-well region, the first
A technique is known in which an output transistor is formed by forming a bipolar transistor as shown in the figure (for example, Japanese Patent Laid-Open No. 130461/1982).

That is, in a CMOS integrated circuit, a P-type diffusion region 2 which becomes a base region is formed on an N-type semiconductor substrate 1 at the same time as the manufacturing process of a P-well region, and an N ⁺ which becomes an emitter region is formed on this P-type diffusion region 2. Region 3 is formed simultaneously with the formation of the source/drain regions. This attempts to construct an NPN type bipolar transistor on a CMOS integrated circuit without changing the process at all.

However, the bipolar transistor with the structure shown in Figure 1 is designed to emphasize the manufacturing process rather than the performance of the transistor, and does not change this, so the operating speed and characteristics of the transistor are inevitably affected. It turns out that there is a problem in that they are considerably inferior to transistors on bipolar integrated circuits.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor technology that exhibits remarkable effects compared to the prior art.

Another object of the present invention is to make it possible to construct bipolar transistors with high operating speed and excellent characteristics on the same semiconductor substrate without changing the manufacturing process of the MOS integrated circuit, for example, when applied to a MOS integrated circuit. The purpose is to

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention provides a CMOS integrated circuit in which polysilicon is formed in two layers.
For example, at the same time as forming contact holes for the source and drain electrodes of an N-channel MOSFET, holes are made in the insulating film in the part that will become the emitter region.
By forming a second polysilicon layer and forming an emitter diffusion layer by diffusion from this polysilicon layer, the emitter region can be formed shallowly.
In addition, by eliminating the need for a mask alignment margin, the above-mentioned object of reducing the emitter size and reducing its parasitic capacitance and improving the operating speed and characteristics of the bibolar transistor is achieved.

The present invention will be specifically explained below using the drawings.

〔Example〕

FIGS. 2 to 5 show an embodiment of the present invention applied to a CMOS integrated circuit in the order of manufacturing steps.

In this embodiment, although not particularly limited, on one semiconductor substrate 1 such as a P-type silicon chip,
forming a P-well region 2 and an N-well region 3;
The steps of forming an N-channel MOSFET and a P-channel MOSFET on the P-well region 2 and N-well region 3, respectively, to obtain the state shown in FIG. 2 are similar to the conventional CMOS process. That is, first, a silicon oxide film is formed on the surface of the semiconductor substrate 1, and photoetching is performed, and an N-channel type is formed using this oxide film as a mask.
A P-well region 2 is formed by diffusing P-type impurities into a location where a MOSFET is to be formed. Similarly,
Using the oxide film as a mask, an N-type impurity is diffused in a location where a P-channel type MOSFET is to be formed, thereby forming an N-well region 3. Incidentally, at this time, an N-well region 3', which becomes a collector region, is simultaneously formed at a location where a bipolar transistor is to be formed.

Then, after thinly oxidizing the substrate surface, Si ₃
An N4 film (silicon nitride film) is formed and photoetched to implant P-type impurity ions for channel stopper into both sides of the P well region 2. After forming a relatively thick field oxide film 4 on the substrate surface using the Si ₃ N 4 film as a mask, the Si ₃ N 4 film is removed and a gate oxide film 5 is formed on the surface, and polysilicon (polysilicon) is formed on the gate oxide film 5. After depositing crystalline silicon, the polysilicon is removed by photoetching except for the gate portion, forming polysilicon gate electrodes 6a and 6b. Thereafter, a SiO ₂ film is deposited on the substrate surface and photoetched, and this SiO ₂ film is used to cover the part where the P-channel MOSFET is to be formed (the surface of the N-well region 3), and an N-type impurity is injected through the oxide film 5. By implanting and thermally diffusing N ⁺ diffusion layers 7a and 7b, which will become the source/drain regions of the N-channel MOSFET. Although not particularly limited, in this embodiment, an N ⁺ diffusion layer 7c, which serves as a pull-up port for the collector of the bipolar transistor, is formed simultaneously with the N ⁺ diffusion layers 7a and 7b, resulting in the state shown in FIG. 2.

After the state shown in Figure 2, it is usually P channel type.
A P ⁺ diffusion layer that will become the source/drain region of the MOSFET is formed. In this example, first, a photoresist or SiO ₂ film is used as a mask to form the part that will become the base region of the bipolar transistor on the surface of the N-well region 3'. A P-type impurity such as boron is implanted and diffused to form a P-type diffusion layer 8. Then, a relatively thin layer of Si ₃ is applied over the entire substrate surface.
After forming an insulating film 9 such as N ₄ film or SiO ₂ film by CVD method (chemical vapor deposition method), an N-channel shape is formed by photoetching.
Contact holes 10a and 10b for source and drain electrodes of the MOSFET are formed. At this time,
At the same time N ⁺ for the collector of the bipolar transistor
The surface of the diffusion layer 7c and the portion of the insulating film 9 that will become the emitter region are also removed to form contact holes 10c and 1.
Open 0d. Thereafter, a polysilicon layer 12 is deposited on the surface of the substrate, resulting in the state shown in FIG.

From this state, N
Source/drain electrode portions 12a, 12b of channel type MOSFET and collector electrode portion 12c and emitter electrode portion 12d of bipolar transistor
Furthermore, a predetermined wiring portion 12e and a resistor portion 12
Remove polysilicon from unnecessary parts except for r. Next, in order to prevent contamination due to ion implantation, the top of the polysilicon layer 12 is thermally oxidized to about 50 to 500%, and when a polysilicon resistor is to be formed, the resistive portion is covered with a photoresist 11'. Type impurities are introduced into the polysilicon layer 12 by ion implantation to lower the resistance. After that,
Heat treatment is performed to form an N-type diffusion layer 13, which will become an emitter region, on the base P-type diffusion layer 8 by diffusion from the polysilicon layer 12. (See Figure 4). At this time, N type impurities enter the collector N ⁺ diffusion layer 7c and the source/drain N ⁺ diffusion layers 7a and 7b by diffusion from the polysilicon layer 12, but the N type impurities are originally in a high concentration. Since it is diffused, it does not affect the characteristics of the transistor.

After the state shown in Figure 4, the N-MOS side and the top of the bipolar transistor are covered with photoresist, and P type impurities are implanted through the thin insulating film 9 and thermally diffused to form the source/drain regions of the P channel ^MOSFET. Form layers 14a and 14b.
Then, a PSG film (phosphorus silicon glass film) 15 is deposited over the entire surface of the substrate by the CVD method, contact holes are formed in the electrode portions of predetermined transistors, and a metal such as aluminum is deposited over the entire surface. Thereafter, an aluminum electrode 16 and an aluminum wiring are formed by photo-etching, and a vacillation film 17 is formed thereon, resulting in a completed state as shown in FIG. However, the N ⁺ diffusion layer 7c for the collector is the N ⁺ diffusion layer 7 for the source/drain of the N-MOS as described above.
Instead of forming the emitter diffusion layer 13 at the same time as the emitter a and 7b, the emitter diffusion layer 13 is formed by diffusion from the polysilicon layer 12.
They may be formed simultaneously.

According to the above embodiment, one mask for forming the P ⁺ diffusion layer 8 which will become the base region is added to the normal CMOS process, and the implantation and diffusion process of the base region and the heat treatment process for forming the emitter region are performed. You can create it just by adding it. Moreover, since the emitter N-type diffusion layer 13 can be formed by diffusion from the polysilicon layer 12, it can be diffused at the same time as the source/drain region (N ⁺ diffusion layer) of the N-channel MOSFET to form a bipolar MOSFET. Compared to the conventional process for forming the emitter region of a transistor, the N-type diffusion layer for the emitter 1
3 can be made shallower. Furthermore, in the conventional process, the emitter region and the N-MOS source region
Since a mask for forming the drain region and a barrel mask for forming the contact hole for the emitter region are required, there must be a margin for fitting both masks, so the area of the emitter region is not made that small. I couldn't do it. On the other hand, in the above embodiment, since the emitter is formed by diffusion from the polysilicon filled in the contact hole, there is no need to provide a margin for mask alignment.

As a result, the size of the emitter region can be reduced to reduce parasitic capacitance, and the overall size of the bipolar transistor can also be reduced, which improves the operating speed and frequency characteristics of the bipolar transistor. do it like this.

In addition, in the above embodiment, the P channel
P ⁺ diffusion layer 14 for MOSFET source/drain
Since a and 14b are formed after the diffusion of the N-type diffusion layer 13 for the emitter of the bipolar transistor, arsenic, which has a high diffusion temperature but can form a shallow N-type diffusion layer, is used as an impurity for the emitter. This can improve the performance of bipolar transistors. In other words, if the P+ diffusion layers 14a and 14b of P-MOS are formed before forming the N-type diffusion layer 13 for the emitter, the P ⁺ diffusion layer 14a and 14b of the P-MOS can be ⁺ Since the impurity diffusion in the diffusion layers 14a and 14b progresses, the emitter region must be formed using phosphorus, which has a low diffusion temperature, as an impurity, and the performance of the bipolar transistor will be inferior to that of the above embodiment.

However, another embodiment of the present invention may include a process in which the source/drain regions of the P-MOS are formed before forming the emitter region of the bipolar transistor by applying the present invention. That is, in this case, in the above embodiment, after forming the N ⁺ diffusion layers 7a and 7b for the source and drain of the N-channel MOSFET and the N-type diffusion layer 7c for the collector of the bipolar transistor, the P-MOSFET is formed.
The side SiO ₂ film is removed, the N-MOS and bipolar transistors are covered with a SiO ₂ film or photoresist, and P type impurities are implanted and diffused to form P ⁺ diffusion layers 14a and 14b. Thereafter, through the same process as in the previous embodiment, an N-type diffusion layer 1 which becomes an emitter region by diffusion from the polysilicon layer 12 is formed.
form 3.

According to such a process, ^the insulating film 9 (Si ₃
(N ₄ film or SiO ₂ film) can be relatively thick. That is, in the embodiment, the insulating film 9
Since the ion implantation of the P ⁺ diffusion layers 14a and 14b for the source and drain of the P-MOS is performed after the formation of the ions, the ions penetrate the insulating film 9 but do not penetrate the polysilicon gate electrodes 6a and 6b. Therefore, the insulating film 9 cannot be made very thick. However, in this second embodiment, the insulating film 9
Since the P ⁺ diffusion layers 14a and 14b for the source and drain of P-MOS are formed before the formation of the insulating film 9
can be made thicker. However, with the current technology, it is relatively difficult to form the insulating film 9 of SiO ₂ which is sufficiently thinner than the polysilicon gate electrodes 6a and 6b. On the other hand, if Si ₃ N ₄ is used, the insulating film 9 is sufficiently thinner than the polysilicon gate electrode.
can be formed.

In the above embodiment, as an example, a polysilicon resistor 12r is formed on an N-channel MOSFET, but this may constitute a memory cell of a static RAM, for example.
This can be used to improve packaging density by stacking a MOS transistor and a load resistor. However, the present invention is not limited to such a configuration.

〔effect〕

(1) At the same time as forming the contact holes for the source and drain electrodes of the N-channel MOSFET, the insulating film in the part that will become the emitter region is removed and the second
Since a second polysilicon layer is formed and an emitter diffusion layer is formed by diffusion from this polysilicon layer, the emitter region can be formed shallowly, and a mask for forming the emitter region and emitter electrode can be formed. By eliminating the need for alignment margin, the emitter size can be reduced, which has the effect of improving the operating speed and frequency characteristics of the transistor.

(2) Form a relatively thin insulating film on the polysilicon gate electrode to insulate it from the second polysilicon layer, and in the process after forming the emitter diffusion layer, diffuse the source and drain of the P-channel MOSFET. Since a layer is formed, even if arsenic, which has a high diffusion temperature, is used as an impurity in the emitter diffusion layer, the source/drain diffusion layer of the P-channel MOSFET will not be expanded when the emitter is formed. This has the effect of improving the characteristics of bipolar transistors and making it possible to short-channel a P-channel MOSFET.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and may be modified in various ways without departing from the gist thereof. Needless to say.

For example, a buried layer may be provided on a semiconductor substrate, an epitaxial layer may be grown thereon, and then a bipolar transistor may be formed on a CMOS device using the same process as in the above embodiment.

Furthermore, the gate electrode of the MOSFET may be formed of a metal layer or a silicide layer.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of a main part of a semiconductor substrate showing an example of the structure of a bipolar transistor in a well-known CMOS integrated circuit, and Figs. 2 to 5 show an example of the structure and its manufacturing method when the present invention is applied to a CMOS integrated circuit FIG. 2 is a cross-sectional view of a main part of the same semiconductor substrate shown in sequence. 1...Semiconductor substrate, 2...P well region, 3...
...N-well region, 4...Field oxide film, 5...
...Gate oxide film, 6a, 6b...Polysilicon gate electrode, 7a, 7b...N-MOS source/drain region (N ⁺ diffusion layer), 8...Base region (P-type diffusion layer for base), 9... ...Insulating film, 10a, 1
0b...Contact hole, 12...Second polysilicon layer, 13...Emitter region (N for emitter)
type diffusion layer), 14a, 14b...P-MOS source/drain region (P ⁺ diffusion layer).

Claims (1)

[Claims] 1. A bipolar transistor formed in a first region of one main surface of a semiconductor substrate;
an insulated gate field effect transistor with a first conductivity type channel formed in the region, and an insulated gate field effect transistor with a second conductivity type channel formed in the third region of the one main surface, The wiring layer connected to the insulated gate field effect transistor of the first conductivity type channel and the conductor layer constituting the emitter electrode of the bipolar transistor are made of a polysilicon layer formed in the same process, and the polysilicon layer is . A semiconductor device, characterized in that the semiconductor device is configured to extend over an insulating film covering a conductor layer constituting a gate electrode of the insulated gate field effect transistor of the first and second conductivity type channels. 2 A bipolar transistor is formed in a first region of one main surface of the semiconductor substrate, an insulated gate field effect transistor of a first conductivity type channel is formed in a second region of the one main surface, and a bipolar transistor is formed in a second region of the one main surface of the semiconductor substrate; An insulated gate field effect transistor of a second conductivity type channel is formed in the third region, an emitter electrode of a polysilicon layer is formed in the bipolar transistor, and a polysilicon layer is formed in the insulated gate field effect transistor of the first conductivity type channel. A method for manufacturing a semiconductor device in which a wiring layer made of a silicon layer is connected, the method comprising: forming an opening for forming an emitter region of the bipolar transistor, and connecting a wiring layer to an insulated gate field effect transistor of the first conductivity type channel. a step of also forming a connection hole; a step of forming a polysilicon layer in the same step for the hole for forming the emitter region and the hole for connecting the wiring layer; and doping impurities into the semiconductor substrate from the polysilicon layer. forming an emitter region by forming an emitter region.